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Searched refs:MAX_CS (Results 1 – 12 of 12) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dxor.c18 static u32 xor_regs_base_backup[MAX_CS];
19 static u32 xor_regs_mask_backup[MAX_CS];
29 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()
31 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()
51 for (ui = 0; ui < MAX_CS; ui++) { in mv_sys_xor_init()
90 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()
92 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()
A Dddr3_spd.c646 if (cs_num > MAX_CS) {
648 MAX_CS, 1);
683 MAX_CS, 1);
896 for (cs = 0; cs < MAX_CS; cs++) {
920 for (cs = 0; cs < MAX_CS; cs++) {
936 for (cs = 0; cs < MAX_CS; cs++) {
1013 for (cs = 0; cs < MAX_CS; cs++) {
1036 for (cs = 0; cs < MAX_CS; cs++) {
1047 for (cs = 0; cs < MAX_CS; cs++) {
1062 for (cs = 0; cs < MAX_CS; cs++) {
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A Dddr3_write_leveling.c54 extern u16 odt_static[ODT_OPT][MAX_CS];
108 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
230 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
432 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
662 u32 res[MAX_CS]; in ddr3_write_leveling_sw()
680 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
723 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
838 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
887 u32 res[MAX_CS]; in ddr3_write_leveling_sw_reg_dimm()
915 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
[all …]
A Dddr3_axp_vars.h41 u16 odt_static[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
60 u16 odt_dynamic[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
A Dddr3_dfs.c44 extern u16 odt_dynamic[ODT_OPT][MAX_CS];
48 extern u16 odt_static[ODT_OPT][MAX_CS];
196 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
442 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
468 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
676 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
1005 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1137 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1163 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1436 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
A Dddr3_axp.h16 #define MAX_CS 4 macro
438 #define MAX_CS 4 macro
A Dddr3_init.c170 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
186 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
233 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_and_set_training_windows()
1074 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_cs_num_from_reg()
A Dddr3_hw_training.h259 u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
260 u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
A Dddr3_dqs.c151 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_rx()
233 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_tx()
1335 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_load_dqs_patterns()
A Dddr3_hw_training.c717 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_training()
1029 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_min_max_read_sample_delay()
A Dddr3_read_leveling.c98 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
A Dddr3_pbs.c1560 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_load_pbs_patterns()

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