Home
last modified time | relevance | path

Searched refs:MAX_INTERFACE_NUM (Results 1 – 11 of 11) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_debug.c114 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_reg_dump()
515 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_print_stability_log()
877 for (i = 0; i < MAX_INTERFACE_NUM; i++) in print_adll()
893 for (i = 0; i < MAX_INTERFACE_NUM; i++) in print_ph()
948 u32 res[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_run_sweep_test()
975 if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_run_sweep_test()
1013 if_id < MAX_INTERFACE_NUM; in ddr3_tip_run_sweep_test()
1061 if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_run_sweep_test()
1094 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_run_leveling_sweep_test()
1095 u32 res[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_run_leveling_sweep_test()
[all …]
A Dddr3_training_pbs.c13 u32 nominal_adll[MAX_INTERFACE_NUM * MAX_BUS_NUM];
19 u8 max_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
20 u8 min_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
21 u8 max_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
22 u8 min_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];
24 u8 adll_shift_lock[MAX_INTERFACE_NUM][MAX_BUS_NUM];
25 u8 adll_shift_val[MAX_INTERFACE_NUM][MAX_BUS_NUM];
27 static u8 pup_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
38 u32 res0[MAX_INTERFACE_NUM]; in ddr3_tip_pbs()
51 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_pbs()
[all …]
A Dddr3_training_leveling.c44 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_read_leveling()
46 u32 data_read[MAX_INTERFACE_NUM + 1] = { 0 }; in ddr3_tip_dynamic_read_leveling()
47 u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()
403 u32 phyreg3_arr[MAX_INTERFACE_NUM][MAX_BUS_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling()
408 u32 data_read[MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling()
410 u32 data2_write[MAX_INTERFACE_NUM][MAX_BUS_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling()
645 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_dynamic_per_bit_read_leveling()
808 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_write_leveling()
809 u32 cs_mask[MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_write_leveling()
815 u32 data_read[MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_write_leveling()
[all …]
A Dddr3_init.h89 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
122 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
156 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
157 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
158 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
160 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
161 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
A Dddr3_training_hw_algo.c18 u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
19 u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
20 u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
21 u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
22 u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
23 u8 interface_state[MAX_INTERFACE_NUM];
24 u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
27 static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];
46 u32 data_read[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_write_additional_odt_setting()
182 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
[all …]
A Dddr3_training_centralization.c21 u32 start_if = 0, end_if = (MAX_INTERFACE_NUM - 1);
24 u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
55 enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()
59 u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
63 u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()
73 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()
80 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
103 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
479 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
506 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_special_rx()
[all …]
A Dddr3_training_ip_engine.c16 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];
18 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *
364 if (interface_num >= MAX_INTERFACE_NUM) { in ddr3_tip_ip_training()
706 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_read_training_result()
738 if (if_id >= MAX_INTERFACE_NUM) { in ddr3_tip_read_training_result()
852 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
912 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_load_pattern_to_mem()
1036 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_ip_training_wrapper_int()
1137 if (if_id >= MAX_INTERFACE_NUM) { in ddr3_tip_ip_training_wrapper()
1154 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_ip_training_wrapper()
[all …]
A Dddr3_training.c350 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller()
366 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
650 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
1021 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_if_polling()
1028 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_if_polling()
1102 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bus_read_modify_write()
1214 u32 cs_mask[MAX_INTERFACE_NUM]; in ddr3_tip_freq_set()
1229 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_freq_set()
1237 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1775 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
[all …]
A Dddr3_training_bist.c78 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_bist_read_result()
127 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in hws_ddr3_run_bist()
186 struct bist_result st_bist_result[MAX_INTERFACE_NUM]; in ddr3_tip_print_bist_res()
190 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()
206 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()
A Dmv_ddr_plat.h12 #define MAX_INTERFACE_NUM 1 macro
A Dmv_ddr_plat.c1408 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_configure_phy()

Completed in 45 milliseconds