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Searched refs:MCTL_CR_CHANNEL (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/arm/mach-sunxi/
A Ddram_sun6i.c273 writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | in mctl_com_init()
376 MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | in sunxi_dram_init()
408 MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | in sunxi_dram_init()
A Ddram_sun8i_a33.c40 MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | in mctl_set_cr()
A Ddram_sun8i_a83t.c39 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun8i_a33.h172 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) macro
A Ddram_sun8i_a83t.h194 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) macro
A Ddram_sun6i.h264 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) macro

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