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Searched refs:MDIO_DEVAD_NONE (Results 1 – 25 of 88) sorted by relevance

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/u-boot/drivers/net/phy/
A Dmarvell.c140 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
141 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
177 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
266 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
277 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
282 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
288 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
294 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
369 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e151x_config()
376 phy_write(phydev, MDIO_DEVAD_NONE, in m88e151x_config()
[all …]
A Dmeson-gxl.c62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in meson_gxl_startup()
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in meson_gxl_startup()
103 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_phy_config()
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_phy_config()
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_phy_config()
106 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_phy_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D); in meson_gxl_phy_config()
110 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417); in meson_gxl_phy_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005); in meson_gxl_phy_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B); in meson_gxl_phy_config()
[all …]
A Dvitesse.c74 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
77 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
132 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
136 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
175 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
182 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8574_config()
201 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
220 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8514_config()
227 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8514_config()
257 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8514_config()
[all …]
A Dca_phy.c32 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0BC6); in __internal_phy_init()
33 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x0053); in __internal_phy_init()
34 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x4003); in __internal_phy_init()
35 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x7e01); in __internal_phy_init()
36 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A42); in __internal_phy_init()
37 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A40); in __internal_phy_init()
38 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x1140); in __internal_phy_init()
45 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90); in __internal_phy_init()
46 data = phy_read(phydev, MDIO_DEVAD_NONE, 19); in __internal_phy_init()
73 val = phy_read(phydev, MDIO_DEVAD_NONE, 27); in __external_phy_init()
[all …]
A Dmscc.c302 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, in vsc8584_cmd()
307 reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE, in vsc8584_cmd()
388 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, in vsc8584_micro_assert_reset()
1023 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
1134 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
1198 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
1204 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
1207 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
1210 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
1215 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
[all …]
A Drealtek.c76 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extread()
81 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in rtl8211f_phy_extread()
90 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extwrite()
162 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211x_config()
218 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
220 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); in rtl8211f_config()
241 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
245 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
248 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
280 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211x_parse_status()
[all …]
A Dbroadcom.c137 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
139 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
149 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, in bcm5482_config()
157 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, in bcm5482_config()
198 phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02); in bcm_cygnus_afe()
201 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1); in bcm_cygnus_afe()
202 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); in bcm_cygnus_afe()
205 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); in bcm_cygnus_afe()
206 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); in bcm_cygnus_afe()
209 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); in bcm_cygnus_afe()
[all …]
A Dnatsemi.c22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
68 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); in dp83865_parse_status()
121 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
A Dmicrel_ksz90x1.c237 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
239 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
310 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
313 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
316 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
319 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
326 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
328 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
330 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
372 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in ksz9031_config()
[all …]
A Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
59 phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG, in et1011c_parse_status()
A Ddavicom.c29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
31 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
/u-boot/board/spear/x600/
A Dx600.c79 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
80 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
86 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); in board_phy_config()
122 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
123 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
126 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); in board_phy_config()
129 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); in board_phy_config()
132 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); in board_phy_config()
/u-boot/board/Marvell/db-mv784mp-gp/
A Ddb-mv784mp-gp.c99 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); in board_phy_config()
101 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); in board_phy_config()
103 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); in board_phy_config()
106 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); in board_phy_config()
108 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); in board_phy_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in board_phy_config()
112 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in board_phy_config()
115 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); in board_phy_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); in board_phy_config()
/u-boot/board/beacon/imx8mn/
A Dimx8mn_beacon.c32 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); in board_phy_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); in board_phy_config()
37 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
38 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()
/u-boot/board/beacon/imx8mm/
A Dimx8mm_beacon.c32 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); in board_phy_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); in board_phy_config()
37 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
38 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()
/u-boot/board/freescale/imx8mm_evk/
A Dimx8mm_evk.c34 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
37 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); in board_phy_config()
38 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); in board_phy_config()
39 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
40 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()
/u-boot/board/k+p/kp_imx6q_tpc/
A Dkp_imx6q_tpc.c58 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8031_phy_fixup()
59 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8031_phy_fixup()
60 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8031_phy_fixup()
62 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8031_phy_fixup()
65 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8031_phy_fixup()
68 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8031_phy_fixup()
69 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8031_phy_fixup()
71 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8031_phy_fixup()
/u-boot/board/compulab/cl-som-imx7/
A Dcl-som-imx7.c139 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in cl_som_imx7_rgmii_rework()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in cl_som_imx7_rgmii_rework()
141 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in cl_som_imx7_rgmii_rework()
142 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
144 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
147 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in cl_som_imx7_rgmii_rework()
151 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
154 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
157 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in cl_som_imx7_rgmii_rework()
158 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in cl_som_imx7_rgmii_rework()
[all …]
/u-boot/drivers/net/pfe_eth/
A Dpfe_mdio.c63 if (dev_addr == MDIO_DEVAD_NONE) { in pfe_phy_read()
74 if (dev_addr == MDIO_DEVAD_NONE) in pfe_phy_read()
117 if (dev_addr == MDIO_DEVAD_NONE) { in pfe_phy_write()
128 if (dev_addr == MDIO_DEVAD_NONE) in pfe_phy_write()
171 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0); in pfe_configure_serdes()
172 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1); in pfe_configure_serdes()
173 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2); in pfe_configure_serdes()
174 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3); in pfe_configure_serdes()
190 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value); in pfe_configure_serdes()
194 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0); in pfe_configure_serdes()
[all …]
/u-boot/board/advantech/imx8qm_rom7720_a1/
A Dimx8qm_rom7720_a1.c82 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
83 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
85 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); in board_phy_config()
86 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); in board_phy_config()
87 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
88 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()
/u-boot/board/freescale/imx8qm_mek/
A Dimx8qm_mek.c70 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
71 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
73 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); in board_phy_config()
74 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); in board_phy_config()
75 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()
/u-boot/board/congatec/cgtqmx6eval/
A Dcgtqmx6eval.c287 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_eth_init()
288 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_eth_init()
336 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in mx6_rgmii_rework()
337 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in mx6_rgmii_rework()
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
383 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in mx6_rgmii_rework()
384 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in mx6_rgmii_rework()
386 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in mx6_rgmii_rework()
389 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb); in mx6_rgmii_rework()
390 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in mx6_rgmii_rework()
[all …]
/u-boot/board/technexion/pico-imx7d/
A Dpico-imx7d.c140 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in board_phy_config()
141 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in board_phy_config()
142 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in board_phy_config()
144 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in board_phy_config()
147 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in board_phy_config()
150 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in board_phy_config()
151 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in board_phy_config()
153 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in board_phy_config()
/u-boot/test/dm/
A Dmdio.c41 ut_assertok(ops->write(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE, in dm_test_mdio()
43 reg = ops->read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE, in dm_test_mdio()
47 ut_assert(ops->read(dev, SANDBOX_PHY_ADDR + 1, MDIO_DEVAD_NONE, in dm_test_mdio()
51 reg = ops->read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE, in dm_test_mdio()
/u-boot/board/google/imx8mq_phanbell/
A Dimx8mq_phanbell.c66 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
67 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
69 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
70 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()

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