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Searched refs:MII_BMCR (Results 1 – 25 of 40) sorted by relevance

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/u-boot/drivers/net/phy/
A Dxilinx_phy.c70 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
123 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_config()
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); in xilinxphy_config()
A Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
A Dnatsemi.c22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
A Dmarvell.c136 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
144 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
485 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1145_config()
487 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1145_config()
586 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1680_config()
588 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1680_config()
A Dphy.c144 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
157 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
167 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
197 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
369 u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_parse_link()
866 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) { in phy_reset()
879 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
881 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
A Ddavicom.c29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
A Dmicrel_ksz90x1.c372 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in ksz9031_config()
374 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr); in ksz9031_config()
481 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in ksz9131_config()
483 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr); in ksz9131_config()
A Daquantia.c483 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
492 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
504 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, in aquantia_config()
539 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
586 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_startup()
A Dbroadcom.c137 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
139 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
A Drealtek.c139 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
216 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211f_config()
A Dmv88e61xx.c591 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR); in mv88e61xx_serdes_init()
595 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val); in mv88e61xx_serdes_init()
840 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR); in mv88e61xx_phy_enable()
844 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val); in mv88e61xx_phy_enable()
/u-boot/drivers/qe/
A Duec_phy.c269 ctrl = uec_phy_read(mii_info, MII_BMCR); in genmii_setup_forced()
299 uec_phy_write(mii_info, MII_BMCR, ctrl); in genmii_setup_forced()
307 ctl = uec_phy_read(mii_info, MII_BMCR); in genmii_restart_aneg()
309 uec_phy_write(mii_info, MII_BMCR, ctl); in genmii_restart_aneg()
347 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in marvell_config_aneg()
526 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in uec_marvell_init()
599 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) | in dm9161_init()
602 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) & in dm9161_init()
917 status = uec_phy_read(mii_info, MII_BMCR); in marvell_phy_interface_mode()
918 uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE); in marvell_phy_interface_mode()
/u-boot/common/
A Dmiiphyutil.c361 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
365 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { in miiphy_reset()
379 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
427 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_speed()
490 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_duplex()
/u-boot/cmd/
A Dmii.c125 { MII_BMCR, reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
217 if ((regno == MII_BMCR) && (pdesc->lo == 6)) { in special_field()
229 else if ((regno == MII_BMCR) && (pdesc->lo == 8)) { in special_field()
/u-boot/board/egnite/ethernut5/
A Dethernut5.c176 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); in board_eth_init()
/u-boot/drivers/net/
A Dag7xxx.c707 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000); in ag933x_phy_setup_wan()
733 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); in ag933x_phy_setup_lan()
792 ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000); in ag953x_phy_setup_wan()
835 ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000); in ag953x_phy_setup_lan()
913 return ag7xxx_switch_write(priv->bus, port, MII_BMCR, in ag933x_phy_setup_reset_set()
916 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, in ag933x_phy_setup_reset_set()
929 ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, &reg); in ag933x_phy_setup_reset_fin()
936 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); in ag933x_phy_setup_reset_fin()
A Dmtk_eth.c692 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7530_setup()
694 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7530_setup()
743 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7530_setup()
745 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7530_setup()
886 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7531_setup()
888 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7531_setup()
937 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7531_setup()
939 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7531_setup()
A Dax88180.c118 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); in ax88180_phy_reset()
121 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) { in ax88180_phy_reset()
353 bmcr_val = ax88180_mdio_read (dev, MII_BMCR); in ax88180_media_config()
A Dmt7620-eth.c481 val = mt7620_mii_read(priv, phy, MII_BMCR); in mt7620_phy_restart_an()
483 mt7620_mii_write(priv, phy, MII_BMCR, val); in mt7620_phy_restart_an()
728 phy_val = mt7620_mii_read(priv, i, MII_BMCR); in mt7620_gsw_config_mt7530()
730 mt7620_mii_write(priv, i, MII_BMCR, phy_val); in mt7620_gsw_config_mt7530()
759 phy_val = mt7620_mii_read(priv, i, MII_BMCR); in mt7620_gsw_config_mt7530()
761 mt7620_mii_write(priv, i, MII_BMCR, phy_val); in mt7620_gsw_config_mt7530()
/u-boot/include/linux/
A Dmii.h13 #define MII_BMCR 0x00 /* Basic mode control register */ macro
A Dmdio.h30 #define MDIO_CTRL1 MII_BMCR
/u-boot/drivers/net/ti/
A Ddavinci_emac.c330 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in gen_auto_negotiate()
335 davinci_eth_phy_write(phy_addr, MII_BMCR, val); in gen_auto_negotiate()
344 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in gen_auto_negotiate()
357 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); in gen_auto_negotiate()
/u-boot/drivers/usb/eth/
A Dmcs7830.c325 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
329 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
333 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
A Dasix.c327 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR); in mii_nway_restart()
331 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); in mii_nway_restart()
408 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); in asix_basic_reset()
/u-boot/board/freescale/mx6qarm2/
A Dmx6qarm2.c196 miiphy_write("FEC", phy, MII_BMCR, 0xa100); in fecmxc_mii_postcall()

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