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Searched refs:MII_CTRL1000 (Results 1 – 15 of 15) sorted by relevance

/u-boot/board/spear/x600/
A Dx600.c86 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
/u-boot/drivers/net/phy/
A Dmicrel_ksz90x1.c285 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); in ksz9021_config()
377 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0); in ksz9031_config()
486 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0); in ksz9131_config()
A Drealtek.c150 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
155 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
A Dphy.c95 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
114 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); in genphy_config_advert()
316 MDIO_DEVAD_NONE, MII_CTRL1000) << 2; in genphy_parse_link()
/u-boot/include/linux/
A Dmii.h20 #define MII_CTRL1000 0x09 /* 1000BASE-T control */ macro
/u-boot/drivers/net/ti/
A Ddavinci_emac.c348 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val); in gen_auto_negotiate()
351 davinci_eth_phy_write(phy_addr, MII_CTRL1000, val); in gen_auto_negotiate()
352 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val); in gen_auto_negotiate()
/u-boot/board/udoo/
A Dudoo.c81 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in mx6_rgmii_rework()
/u-boot/drivers/net/
A Dravb.c336 reg = phy_read(phydev, -1, MII_CTRL1000); in ravb_phy_config()
338 phy_write(phydev, -1, MII_CTRL1000, reg); in ravb_phy_config()
A Dbcm6368-eth.c278 port->phy_id, MII_CTRL1000); in bcm6368_eth_adjust_link()
A Dag7xxx.c900 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000, in ag933x_phy_setup_reset_set()
905 ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000, in ag933x_phy_setup_reset_set()
/u-boot/drivers/qe/
A Duec_phy.c322 adv = uec_phy_read(mii_info, MII_CTRL1000); in gbit_config_aneg()
329 uec_phy_write(mii_info, MII_CTRL1000, adv); in gbit_config_aneg()
/u-boot/cmd/
A Dmii.c137 { MII_CTRL1000, reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
/u-boot/drivers/usb/eth/
A Dr8152.h536 #define MII_CTRL1000 0x09 /* 1000BASE-T control */ macro
A Dasix88179.c360 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); in asix_basic_reset()
A Dr8152.c1043 gbcr = r8152_mdio_read(tp, MII_CTRL1000); in rtl8152_set_speed()
1097 r8152_mdio_write(tp, MII_CTRL1000, gbcr); in rtl8152_set_speed()

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