1 /*
2 * Synopsys HSDK SDP CGU clock driver
3 *
4 * Copyright (C) 2017 Synopsys
5 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <common.h>
13 #include <clk-uclass.h>
14 #include <div64.h>
15 #include <dm.h>
16 #include <log.h>
17 #include <linux/bitops.h>
18 #include <linux/bug.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <asm/arcregs.h>
22
23 #include <dt-bindings/clock/snps,hsdk-cgu.h>
24
25 /*
26 * Synopsys ARC HSDK clock tree.
27 *
28 * ------------------
29 * | 33.33 MHz xtal |
30 * ------------------
31 * |
32 * | -----------
33 * |-->| ARC PLL |
34 * | -----------
35 * | |
36 * | |-->|CGU_ARC_IDIV|----------->
37 * | |-->|CREG_CORE_IF_DIV|------->
38 * |
39 * | --------------
40 * |-->| SYSTEM PLL |
41 * | --------------
42 * | |
43 * | |-->|CGU_SYS_IDIV_APB|------->
44 * | |-->|CGU_SYS_IDIV_AXI|------->
45 * | |-->|CGU_SYS_IDIV_*|--------->
46 * | |-->|CGU_SYS_IDIV_EBI_REF|--->
47 * |
48 * | --------------
49 * |-->| TUNNEL PLL |
50 * | --------------
51 * | |
52 * | |-->|CGU_TUN_IDIV_TUN|----------->
53 * | |-->|CGU_TUN_IDIV_ROM|----------->
54 * | |-->|CGU_TUN_IDIV_PWM|----------->
55 * |
56 * | -----------
57 * |-->| DDR PLL |
58 * -----------
59 * |
60 * |---------------------------->
61 *
62 * ------------------
63 * | 27.00 MHz xtal |
64 * ------------------
65 * |
66 * | ------------
67 * |-->| HDMI PLL |
68 * ------------
69 * |
70 * |-->|CGU_HDMI_IDIV_APB|------>
71 */
72
73 #define CGU_ARC_IDIV 0x080
74 #define CGU_TUN_IDIV_TUN 0x380
75 #define CGU_TUN_IDIV_ROM 0x390
76 #define CGU_TUN_IDIV_PWM 0x3A0
77 #define CGU_TUN_IDIV_TIMER 0x3B0
78 #define CGU_HDMI_IDIV_APB 0x480
79 #define CGU_SYS_IDIV_APB 0x180
80 #define CGU_SYS_IDIV_AXI 0x190
81 #define CGU_SYS_IDIV_ETH 0x1A0
82 #define CGU_SYS_IDIV_USB 0x1B0
83 #define CGU_SYS_IDIV_SDIO 0x1C0
84 #define CGU_SYS_IDIV_HDMI 0x1D0
85 #define CGU_SYS_IDIV_GFX_CORE 0x1E0
86 #define CGU_SYS_IDIV_GFX_DMA 0x1F0
87 #define CGU_SYS_IDIV_GFX_CFG 0x200
88 #define CGU_SYS_IDIV_DMAC_CORE 0x210
89 #define CGU_SYS_IDIV_DMAC_CFG 0x220
90 #define CGU_SYS_IDIV_SDIO_REF 0x230
91 #define CGU_SYS_IDIV_SPI_REF 0x240
92 #define CGU_SYS_IDIV_I2C_REF 0x250
93 #define CGU_SYS_IDIV_UART_REF 0x260
94 #define CGU_SYS_IDIV_EBI_REF 0x270
95
96 #define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
97
98 #define CGU_ARC_PLL 0x0
99 #define CGU_SYS_PLL 0x10
100 #define CGU_DDR_PLL 0x20
101 #define CGU_TUN_PLL 0x30
102 #define CGU_HDMI_PLL 0x40
103
104 #define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
105 #define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
106 #define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
107 #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
108
109 #define CGU_PLL_CTRL_ODIV_SHIFT 2
110 #define CGU_PLL_CTRL_IDIV_SHIFT 4
111 #define CGU_PLL_CTRL_FBDIV_SHIFT 9
112 #define CGU_PLL_CTRL_BAND_SHIFT 20
113
114 #define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
115 #define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
116 #define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
117
118 #define CGU_PLL_CTRL_PD BIT(0)
119 #define CGU_PLL_CTRL_BYPASS BIT(1)
120
121 #define CGU_PLL_STATUS_LOCK BIT(0)
122 #define CGU_PLL_STATUS_ERR BIT(1)
123
124 #define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
125
126 #define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
127 #define CORE_IF_CLK_THRESHOLD_HZ 500000000
128 #define CREG_CORE_IF_CLK_DIV_1 0x0
129 #define CREG_CORE_IF_CLK_DIV_2 0x1
130
131 #define MIN_PLL_RATE 100000000 /* 100 MHz */
132 #define PARENT_RATE_33 33333333 /* fixed clock - xtal */
133 #define PARENT_RATE_27 27000000 /* fixed clock - xtal */
134 #define CGU_MAX_CLOCKS 27
135
136 #define MAX_FREQ_VARIATIONS 6
137
138 struct hsdk_idiv_cfg {
139 const u32 oft;
140 const u8 val[MAX_FREQ_VARIATIONS];
141 };
142
143 struct hsdk_div_full_cfg {
144 const u32 clk_rate[MAX_FREQ_VARIATIONS];
145 const u32 pll_rate[MAX_FREQ_VARIATIONS];
146 const struct hsdk_idiv_cfg idiv[];
147 };
148
149 static const struct hsdk_div_full_cfg hsdk_4xd_tun_clk_cfg = {
150 { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
151 { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
152 { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
153 { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
154 { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
155 { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } },
156 { /* last one */ }
157 }
158 };
159
160 static const struct hsdk_div_full_cfg hsdk_tun_clk_cfg = {
161 { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
162 { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
163 { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
164 { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
165 { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
166 { /* last one */ }
167 }
168 };
169
170 static const struct hsdk_div_full_cfg axi_clk_cfg = {
171 { 200000000, 400000000, 600000000, 800000000 },
172 { 800000000, 800000000, 600000000, 800000000 }, {
173 { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
174 { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
175 { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
176 { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
177 { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
178 { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
179 { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
180 { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
181 { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
182 { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
183 { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
184 { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
185 { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
186 { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
187 { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
188 { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } }, /* EBI-REF */
189 { /* last one */ }
190 }
191 };
192
193 struct hsdk_pll_cfg {
194 const u32 rate;
195 const u8 idiv;
196 const u8 fbdiv;
197 const u8 odiv;
198 const u8 band;
199 };
200
201 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
202 { 100000000, 0, 11, 3, 0 },
203 { 125000000, 0, 14, 3, 0 },
204 { 133000000, 0, 15, 3, 0 },
205 { 150000000, 0, 17, 3, 0 },
206 { 200000000, 1, 47, 3, 0 },
207 { 233000000, 1, 27, 2, 0 },
208 { 300000000, 1, 35, 2, 0 },
209 { 333000000, 1, 39, 2, 0 },
210 { 400000000, 1, 47, 2, 0 },
211 { 500000000, 0, 14, 1, 0 },
212 { 600000000, 0, 17, 1, 0 },
213 { 700000000, 0, 20, 1, 0 },
214 { 750000000, 1, 44, 1, 0 },
215 { 800000000, 0, 23, 1, 0 },
216 { 900000000, 1, 26, 0, 0 },
217 { 1000000000, 1, 29, 0, 0 },
218 { 1100000000, 1, 32, 0, 0 },
219 { 1200000000, 1, 35, 0, 0 },
220 { 1300000000, 1, 38, 0, 0 },
221 { 1400000000, 1, 41, 0, 0 },
222 { 1500000000, 1, 44, 0, 0 },
223 { 1600000000, 1, 47, 0, 0 },
224 {}
225 };
226
227 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
228 { 297000000, 0, 21, 2, 0 },
229 { 540000000, 0, 19, 1, 0 },
230 { 594000000, 0, 21, 1, 0 },
231 {}
232 };
233
234 struct hsdk_cgu_domain {
235 /* PLLs registers */
236 void __iomem *pll_regs;
237 /* PLLs special registers */
238 void __iomem *spec_regs;
239 /* PLLs devdata */
240 const struct hsdk_pll_devdata *pll;
241
242 /* Dividers registers */
243 void __iomem *idiv_regs;
244 };
245
246 struct hsdk_cgu_clk {
247 const struct cgu_clk_map *map;
248 /* CGU block register */
249 void __iomem *cgu_regs;
250 /* CREG block register */
251 void __iomem *creg_regs;
252
253 /* The domain we are working with */
254 struct hsdk_cgu_domain curr_domain;
255 };
256
257 struct hsdk_pll_devdata {
258 const u32 parent_rate;
259 const struct hsdk_pll_cfg *const pll_cfg;
260 const int (*const update_rate)(struct hsdk_cgu_clk *clk,
261 unsigned long rate,
262 const struct hsdk_pll_cfg *cfg);
263 };
264
265 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
266 const struct hsdk_pll_cfg *);
267 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
268 const struct hsdk_pll_cfg *);
269
270 static const struct hsdk_pll_devdata core_pll_dat = {
271 .parent_rate = PARENT_RATE_33,
272 .pll_cfg = asdt_pll_cfg,
273 .update_rate = hsdk_pll_core_update_rate,
274 };
275
276 static const struct hsdk_pll_devdata sdt_pll_dat = {
277 .parent_rate = PARENT_RATE_33,
278 .pll_cfg = asdt_pll_cfg,
279 .update_rate = hsdk_pll_comm_update_rate,
280 };
281
282 static const struct hsdk_pll_devdata hdmi_pll_dat = {
283 .parent_rate = PARENT_RATE_27,
284 .pll_cfg = hdmi_pll_cfg,
285 .update_rate = hsdk_pll_comm_update_rate,
286 };
287
288 static ulong idiv_set(struct clk *, ulong);
289 static ulong cpu_clk_set(struct clk *, ulong);
290 static ulong axi_clk_set(struct clk *, ulong);
291 static ulong tun_hsdk_set(struct clk *, ulong);
292 static ulong tun_h4xd_set(struct clk *, ulong);
293 static ulong idiv_get(struct clk *);
294 static int idiv_off(struct clk *);
295 static ulong pll_set(struct clk *, ulong);
296 static ulong pll_get(struct clk *);
297
298 struct cgu_clk_map {
299 const u32 cgu_pll_oft;
300 const u32 cgu_div_oft;
301 const struct hsdk_pll_devdata *const pll_devdata;
302 const ulong (*const get_rate)(struct clk *clk);
303 const ulong (*const set_rate)(struct clk *clk, ulong rate);
304 const int (*const disable)(struct clk *clk);
305 };
306
307 static const struct cgu_clk_map hsdk_clk_map[] = {
308 [CLK_ARC_PLL] = { CGU_ARC_PLL, 0, &core_pll_dat, pll_get, pll_set, NULL },
309 [CLK_ARC] = { CGU_ARC_PLL, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
310 [CLK_DDR_PLL] = { CGU_DDR_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
311 [CLK_SYS_PLL] = { CGU_SYS_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
312 [CLK_SYS_APB] = { CGU_SYS_PLL, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
313 [CLK_SYS_AXI] = { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
314 [CLK_SYS_ETH] = { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
315 [CLK_SYS_USB] = { CGU_SYS_PLL, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
316 [CLK_SYS_SDIO] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
317 [CLK_SYS_HDMI] = { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
318 [CLK_SYS_GFX_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
319 [CLK_SYS_GFX_DMA] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
320 [CLK_SYS_GFX_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
321 [CLK_SYS_DMAC_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
322 [CLK_SYS_DMAC_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
323 [CLK_SYS_SDIO_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
324 [CLK_SYS_SPI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
325 [CLK_SYS_I2C_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
326 [CLK_SYS_UART_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
327 [CLK_SYS_EBI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
328 [CLK_TUN_PLL] = { CGU_TUN_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
329 [CLK_TUN_TUN] = { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_hsdk_set, idiv_off },
330 [CLK_TUN_ROM] = { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
331 [CLK_TUN_PWM] = { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
332 [CLK_TUN_TIMER] = { /* missing in HSDK */ },
333 [CLK_HDMI_PLL] = { CGU_HDMI_PLL, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
334 [CLK_HDMI] = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
335 };
336
337 static const struct cgu_clk_map hsdk_4xd_clk_map[] = {
338 [CLK_ARC_PLL] = { CGU_ARC_PLL, 0, &core_pll_dat, pll_get, pll_set, NULL },
339 [CLK_ARC] = { CGU_ARC_PLL, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
340 [CLK_DDR_PLL] = { CGU_DDR_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
341 [CLK_SYS_PLL] = { CGU_SYS_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
342 [CLK_SYS_APB] = { CGU_SYS_PLL, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
343 [CLK_SYS_AXI] = { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
344 [CLK_SYS_ETH] = { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
345 [CLK_SYS_USB] = { CGU_SYS_PLL, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
346 [CLK_SYS_SDIO] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
347 [CLK_SYS_HDMI] = { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
348 [CLK_SYS_GFX_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
349 [CLK_SYS_GFX_DMA] = { /* missing in HSDK-4xD */ },
350 [CLK_SYS_GFX_CFG] = { /* missing in HSDK-4xD */ },
351 [CLK_SYS_DMAC_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
352 [CLK_SYS_DMAC_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
353 [CLK_SYS_SDIO_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
354 [CLK_SYS_SPI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
355 [CLK_SYS_I2C_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
356 [CLK_SYS_UART_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
357 [CLK_SYS_EBI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
358 [CLK_TUN_PLL] = { CGU_TUN_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
359 [CLK_TUN_TUN] = { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_h4xd_set, idiv_off },
360 [CLK_TUN_ROM] = { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
361 [CLK_TUN_PWM] = { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
362 [CLK_TUN_TIMER] = { CGU_TUN_PLL, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
363 [CLK_HDMI_PLL] = { CGU_HDMI_PLL, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
364 [CLK_HDMI] = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
365 };
366
hsdk_idiv_write(struct hsdk_cgu_clk * clk,u32 val)367 static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
368 {
369 iowrite32(val, clk->curr_domain.idiv_regs);
370 }
371
hsdk_idiv_read(struct hsdk_cgu_clk * clk)372 static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
373 {
374 return ioread32(clk->curr_domain.idiv_regs);
375 }
376
hsdk_pll_write(struct hsdk_cgu_clk * clk,u32 reg,u32 val)377 static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
378 {
379 iowrite32(val, clk->curr_domain.pll_regs + reg);
380 }
381
hsdk_pll_read(struct hsdk_cgu_clk * clk,u32 reg)382 static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
383 {
384 return ioread32(clk->curr_domain.pll_regs + reg);
385 }
386
hsdk_pll_spcwrite(struct hsdk_cgu_clk * clk,u32 reg,u32 val)387 static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
388 {
389 iowrite32(val, clk->curr_domain.spec_regs + reg);
390 }
391
hsdk_pll_spcread(struct hsdk_cgu_clk * clk,u32 reg)392 static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
393 {
394 return ioread32(clk->curr_domain.spec_regs + reg);
395 }
396
hsdk_pll_set_cfg(struct hsdk_cgu_clk * clk,const struct hsdk_pll_cfg * cfg)397 static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
398 const struct hsdk_pll_cfg *cfg)
399 {
400 u32 val = 0;
401
402 /* Powerdown and Bypass bits should be cleared */
403 val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
404 val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
405 val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
406 val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
407
408 pr_debug("write configurarion: %#x\n", val);
409
410 hsdk_pll_write(clk, CGU_PLL_CTRL, val);
411 }
412
hsdk_pll_is_locked(struct hsdk_cgu_clk * clk)413 static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
414 {
415 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
416 }
417
hsdk_pll_is_err(struct hsdk_cgu_clk * clk)418 static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
419 {
420 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
421 }
422
pll_get(struct clk * sclk)423 static ulong pll_get(struct clk *sclk)
424 {
425 u32 val;
426 u64 rate;
427 u32 idiv, fbdiv, odiv;
428 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
429 u32 parent_rate = clk->curr_domain.pll->parent_rate;
430
431 val = hsdk_pll_read(clk, CGU_PLL_CTRL);
432
433 pr_debug("current configurarion: %#x\n", val);
434
435 /* Check if PLL is bypassed */
436 if (val & CGU_PLL_CTRL_BYPASS)
437 return parent_rate;
438
439 /* Check if PLL is disabled */
440 if (val & CGU_PLL_CTRL_PD)
441 return 0;
442
443 /* input divider = reg.idiv + 1 */
444 idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
445 /* fb divider = 2*(reg.fbdiv + 1) */
446 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
447 /* output divider = 2^(reg.odiv) */
448 odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
449
450 rate = (u64)parent_rate * fbdiv;
451 do_div(rate, idiv * odiv);
452
453 return rate;
454 }
455
hsdk_pll_round_rate(struct clk * sclk,unsigned long rate)456 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
457 {
458 int i;
459 unsigned long best_rate;
460 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
461 const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
462
463 if (pll_cfg[0].rate == 0)
464 return -EINVAL;
465
466 best_rate = pll_cfg[0].rate;
467
468 for (i = 1; pll_cfg[i].rate != 0; i++) {
469 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
470 best_rate = pll_cfg[i].rate;
471 }
472
473 pr_debug("chosen best rate: %lu\n", best_rate);
474
475 return best_rate;
476 }
477
hsdk_pll_comm_update_rate(struct hsdk_cgu_clk * clk,unsigned long rate,const struct hsdk_pll_cfg * cfg)478 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
479 unsigned long rate,
480 const struct hsdk_pll_cfg *cfg)
481 {
482 hsdk_pll_set_cfg(clk, cfg);
483
484 /*
485 * Wait until CGU relocks and check error status.
486 * If after timeout CGU is unlocked yet return error.
487 */
488 udelay(HSDK_PLL_MAX_LOCK_TIME);
489 if (!hsdk_pll_is_locked(clk))
490 return -ETIMEDOUT;
491
492 if (hsdk_pll_is_err(clk))
493 return -EINVAL;
494
495 return 0;
496 }
497
hsdk_pll_core_update_rate(struct hsdk_cgu_clk * clk,unsigned long rate,const struct hsdk_pll_cfg * cfg)498 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
499 unsigned long rate,
500 const struct hsdk_pll_cfg *cfg)
501 {
502 /*
503 * When core clock exceeds 500MHz, the divider for the interface
504 * clock must be programmed to div-by-2.
505 */
506 if (rate > CORE_IF_CLK_THRESHOLD_HZ)
507 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
508
509 hsdk_pll_set_cfg(clk, cfg);
510
511 /*
512 * Wait until CGU relocks and check error status.
513 * If after timeout CGU is unlocked yet return error.
514 */
515 udelay(HSDK_PLL_MAX_LOCK_TIME);
516 if (!hsdk_pll_is_locked(clk))
517 return -ETIMEDOUT;
518
519 if (hsdk_pll_is_err(clk))
520 return -EINVAL;
521
522 /*
523 * Program divider to div-by-1 if we succesfuly set core clock below
524 * 500MHz threshold.
525 */
526 if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
527 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
528
529 return 0;
530 }
531
pll_set(struct clk * sclk,ulong rate)532 static ulong pll_set(struct clk *sclk, ulong rate)
533 {
534 int i;
535 unsigned long best_rate;
536 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
537 const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
538 const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
539
540 best_rate = hsdk_pll_round_rate(sclk, rate);
541
542 for (i = 0; pll_cfg[i].rate != 0; i++)
543 if (pll_cfg[i].rate == best_rate)
544 return pll->update_rate(clk, best_rate, &pll_cfg[i]);
545
546 pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
547 pll->parent_rate);
548
549 return -EINVAL;
550 }
551
idiv_off(struct clk * sclk)552 static int idiv_off(struct clk *sclk)
553 {
554 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
555
556 hsdk_idiv_write(clk, 0);
557
558 return 0;
559 }
560
idiv_get(struct clk * sclk)561 static ulong idiv_get(struct clk *sclk)
562 {
563 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
564 ulong parent_rate = pll_get(sclk);
565 u32 div_factor = hsdk_idiv_read(clk);
566
567 div_factor &= CGU_IDIV_MASK;
568
569 pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
570
571 if (div_factor == 0)
572 return 0;
573
574 return parent_rate / div_factor;
575 }
576
577 /* Special behavior: wen we set this clock we set both idiv and pll */
cpu_clk_set(struct clk * sclk,ulong rate)578 static ulong cpu_clk_set(struct clk *sclk, ulong rate)
579 {
580 ulong ret;
581
582 ret = pll_set(sclk, rate);
583 idiv_set(sclk, rate);
584
585 return ret;
586 }
587
588 /*
589 * Special behavior:
590 * when we set these clocks we set both PLL and all idiv dividers related to
591 * this PLL domain.
592 */
common_div_clk_set(struct clk * sclk,ulong rate,const struct hsdk_div_full_cfg * cfg)593 static ulong common_div_clk_set(struct clk *sclk, ulong rate,
594 const struct hsdk_div_full_cfg *cfg)
595 {
596 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
597 ulong pll_rate;
598 int i, freq_idx = -1;
599 ulong ret = 0;
600
601 pll_rate = pll_get(sclk);
602
603 for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
604 /* unused freq variations are filled with 0 */
605 if (!cfg->clk_rate[i])
606 break;
607
608 if (cfg->clk_rate[i] == rate) {
609 freq_idx = i;
610 break;
611 }
612 }
613
614 if (freq_idx < 0) {
615 pr_err("clk: invalid rate=%ld Hz\n", rate);
616 return -EINVAL;
617 }
618
619 /* configure PLL before dividers */
620 if (cfg->pll_rate[freq_idx] < pll_rate)
621 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
622
623 /* configure SYS dividers */
624 for (i = 0; cfg->idiv[i].oft != 0; i++) {
625 clk->curr_domain.idiv_regs = clk->cgu_regs + cfg->idiv[i].oft;
626 hsdk_idiv_write(clk, cfg->idiv[i].val[freq_idx]);
627 }
628
629 /* configure PLL after dividers */
630 if (cfg->pll_rate[freq_idx] >= pll_rate)
631 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
632
633 return ret;
634 }
635
axi_clk_set(struct clk * sclk,ulong rate)636 static ulong axi_clk_set(struct clk *sclk, ulong rate)
637 {
638 return common_div_clk_set(sclk, rate, &axi_clk_cfg);
639 }
640
tun_hsdk_set(struct clk * sclk,ulong rate)641 static ulong tun_hsdk_set(struct clk *sclk, ulong rate)
642 {
643 return common_div_clk_set(sclk, rate, &hsdk_tun_clk_cfg);
644 }
645
tun_h4xd_set(struct clk * sclk,ulong rate)646 static ulong tun_h4xd_set(struct clk *sclk, ulong rate)
647 {
648 return common_div_clk_set(sclk, rate, &hsdk_4xd_tun_clk_cfg);
649 }
650
idiv_set(struct clk * sclk,ulong rate)651 static ulong idiv_set(struct clk *sclk, ulong rate)
652 {
653 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
654 ulong parent_rate = pll_get(sclk);
655 u32 div_factor;
656
657 div_factor = parent_rate / rate;
658 if (abs(rate - parent_rate / (div_factor + 1)) <=
659 abs(rate - parent_rate / div_factor)) {
660 div_factor += 1;
661 }
662
663 if (div_factor & ~CGU_IDIV_MASK) {
664 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
665 rate, parent_rate, div_factor, CGU_IDIV_MASK);
666
667 div_factor = CGU_IDIV_MASK;
668 }
669
670 if (div_factor == 0) {
671 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
672 rate, parent_rate, div_factor);
673
674 div_factor = 1;
675 }
676
677 hsdk_idiv_write(clk, div_factor);
678
679 return 0;
680 }
681
hsdk_prepare_clock_tree_branch(struct clk * sclk)682 static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
683 {
684 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
685
686 if (sclk->id >= CGU_MAX_CLOCKS)
687 return -EINVAL;
688
689 /* clocks missing in current map have their entry zeroed */
690 if (!clk->map[sclk->id].pll_devdata)
691 return -EINVAL;
692
693 clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
694 clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft;
695 clk->curr_domain.spec_regs = clk->creg_regs;
696 clk->curr_domain.idiv_regs = clk->cgu_regs + clk->map[sclk->id].cgu_div_oft;
697
698 return 0;
699 }
700
hsdk_cgu_get_rate(struct clk * sclk)701 static ulong hsdk_cgu_get_rate(struct clk *sclk)
702 {
703 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
704
705 if (hsdk_prepare_clock_tree_branch(sclk))
706 return -EINVAL;
707
708 return clk->map[sclk->id].get_rate(sclk);
709 }
710
hsdk_cgu_set_rate(struct clk * sclk,ulong rate)711 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
712 {
713 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
714
715 if (hsdk_prepare_clock_tree_branch(sclk))
716 return -EINVAL;
717
718 if (clk->map[sclk->id].set_rate)
719 return clk->map[sclk->id].set_rate(sclk, rate);
720
721 return -ENOTSUPP;
722 }
723
hsdk_cgu_disable(struct clk * sclk)724 static int hsdk_cgu_disable(struct clk *sclk)
725 {
726 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
727
728 if (hsdk_prepare_clock_tree_branch(sclk))
729 return -EINVAL;
730
731 if (clk->map[sclk->id].disable)
732 return clk->map[sclk->id].disable(sclk);
733
734 return -ENOTSUPP;
735 }
736
737 static const struct clk_ops hsdk_cgu_ops = {
738 .set_rate = hsdk_cgu_set_rate,
739 .get_rate = hsdk_cgu_get_rate,
740 .disable = hsdk_cgu_disable,
741 };
742
hsdk_cgu_clk_probe(struct udevice * dev)743 static int hsdk_cgu_clk_probe(struct udevice *dev)
744 {
745 struct hsdk_cgu_clk *hsdk_clk = dev_get_priv(dev);
746
747 BUILD_BUG_ON(ARRAY_SIZE(hsdk_clk_map) != CGU_MAX_CLOCKS);
748 BUILD_BUG_ON(ARRAY_SIZE(hsdk_4xd_clk_map) != CGU_MAX_CLOCKS);
749
750 /* Choose which clock map to use in runtime */
751 if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF) == 0x52)
752 hsdk_clk->map = hsdk_clk_map;
753 else
754 hsdk_clk->map = hsdk_4xd_clk_map;
755
756 hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
757 if (!hsdk_clk->cgu_regs)
758 return -EINVAL;
759
760 hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
761 if (!hsdk_clk->creg_regs)
762 return -EINVAL;
763
764 return 0;
765 }
766
767 static const struct udevice_id hsdk_cgu_clk_id[] = {
768 { .compatible = "snps,hsdk-cgu-clock" },
769 { }
770 };
771
772 U_BOOT_DRIVER(hsdk_cgu_clk) = {
773 .name = "hsdk-cgu-clk",
774 .id = UCLASS_CLK,
775 .of_match = hsdk_cgu_clk_id,
776 .probe = hsdk_cgu_clk_probe,
777 .priv_auto = sizeof(struct hsdk_cgu_clk),
778 .ops = &hsdk_cgu_ops,
779 };
780