1 /* 2 * PowerPC memory management structures 3 */ 4 5 #ifndef _PPC_MMU_H_ 6 #define _PPC_MMU_H_ 7 8 #ifndef __ASSEMBLY__ 9 /* Hardware Page Table Entry */ 10 #include <linux/bitops.h> 11 typedef struct _PTE { 12 #ifdef CONFIG_PPC64BRIDGE 13 unsigned long long vsid:52; 14 unsigned long api:5; 15 unsigned long :5; 16 unsigned long h:1; 17 unsigned long v:1; 18 unsigned long long rpn:52; 19 #else /* CONFIG_PPC64BRIDGE */ 20 unsigned long v:1; /* Entry is valid */ 21 unsigned long vsid:24; /* Virtual segment identifier */ 22 unsigned long h:1; /* Hash algorithm indicator */ 23 unsigned long api:6; /* Abbreviated page index */ 24 unsigned long rpn:20; /* Real (physical) page number */ 25 #endif /* CONFIG_PPC64BRIDGE */ 26 unsigned long :3; /* Unused */ 27 unsigned long r:1; /* Referenced */ 28 unsigned long c:1; /* Changed */ 29 unsigned long w:1; /* Write-thru cache mode */ 30 unsigned long i:1; /* Cache inhibited */ 31 unsigned long m:1; /* Memory coherence */ 32 unsigned long g:1; /* Guarded */ 33 unsigned long :1; /* Unused */ 34 unsigned long pp:2; /* Page protection */ 35 } PTE; 36 37 /* Values for PP (assumes Ks=0, Kp=1) */ 38 #define PP_RWXX 0 /* Supervisor read/write, User none */ 39 #define PP_RWRX 1 /* Supervisor read/write, User read */ 40 #define PP_RWRW 2 /* Supervisor read/write, User read/write */ 41 #define PP_RXRX 3 /* Supervisor read, User read */ 42 43 /* Segment Register */ 44 typedef struct _SEGREG { 45 unsigned long t:1; /* Normal or I/O type */ 46 unsigned long ks:1; /* Supervisor 'key' (normally 0) */ 47 unsigned long kp:1; /* User 'key' (normally 1) */ 48 unsigned long n:1; /* No-execute */ 49 unsigned long :4; /* Unused */ 50 unsigned long vsid:24; /* Virtual Segment Identifier */ 51 } SEGREG; 52 53 /* Block Address Translation (BAT) Registers */ 54 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ 55 unsigned long bepi:15; /* Effective page index (virtual address) */ 56 unsigned long :8; /* unused */ 57 unsigned long w:1; 58 unsigned long i:1; /* Cache inhibit */ 59 unsigned long m:1; /* Memory coherence */ 60 unsigned long ks:1; /* Supervisor key (normally 0) */ 61 unsigned long kp:1; /* User key (normally 1) */ 62 unsigned long pp:2; /* Page access protections */ 63 } P601_BATU; 64 65 typedef struct _BATU { /* Upper part of BAT (all except 601) */ 66 #ifdef CONFIG_PPC64BRIDGE 67 unsigned long long bepi:47; 68 #else /* CONFIG_PPC64BRIDGE */ 69 unsigned long bepi:15; /* Effective page index (virtual address) */ 70 #endif /* CONFIG_PPC64BRIDGE */ 71 unsigned long :4; /* Unused */ 72 unsigned long bl:11; /* Block size mask */ 73 unsigned long vs:1; /* Supervisor valid */ 74 unsigned long vp:1; /* User valid */ 75 } BATU; 76 77 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ 78 unsigned long brpn:15; /* Real page index (physical address) */ 79 unsigned long :10; /* Unused */ 80 unsigned long v:1; /* Valid bit */ 81 unsigned long bl:6; /* Block size mask */ 82 } P601_BATL; 83 84 typedef struct _BATL { /* Lower part of BAT (all except 601) */ 85 #ifdef CONFIG_PPC64BRIDGE 86 unsigned long long brpn:47; 87 #else /* CONFIG_PPC64BRIDGE */ 88 unsigned long brpn:15; /* Real page index (physical address) */ 89 #endif /* CONFIG_PPC64BRIDGE */ 90 unsigned long :10; /* Unused */ 91 unsigned long w:1; /* Write-thru cache */ 92 unsigned long i:1; /* Cache inhibit */ 93 unsigned long m:1; /* Memory coherence */ 94 unsigned long g:1; /* Guarded (MBZ in IBAT) */ 95 unsigned long :1; /* Unused */ 96 unsigned long pp:2; /* Page access protections */ 97 } BATL; 98 99 typedef struct _BAT { 100 BATU batu; /* Upper register */ 101 BATL batl; /* Lower register */ 102 } BAT; 103 104 typedef struct _P601_BAT { 105 P601_BATU batu; /* Upper register */ 106 P601_BATL batl; /* Lower register */ 107 } P601_BAT; 108 109 /* 110 * Simulated two-level MMU. This structure is used by the kernel 111 * to keep track of MMU mappings and is used to update/maintain 112 * the hardware HASH table which is really a cache of mappings. 113 * 114 * The simulated structures mimic the hardware available on other 115 * platforms, notably the 80x86 and 680x0. 116 */ 117 118 typedef struct _pte { 119 unsigned long page_num:20; 120 unsigned long flags:12; /* Page flags (some unused bits) */ 121 } pte; 122 123 #define PD_SHIFT (10+12) /* Page directory */ 124 #define PD_MASK 0x02FF 125 #define PT_SHIFT (12) /* Page Table */ 126 #define PT_MASK 0x02FF 127 #define PG_SHIFT (12) /* Page Entry */ 128 129 130 /* MMU context */ 131 132 typedef struct _MMU_context { 133 SEGREG segs[16]; /* Segment registers */ 134 pte **pmap; /* Two-level page-map structure */ 135 } MMU_context; 136 137 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 138 extern void _tlbia(void); /* invalidate all TLB entries */ 139 140 #ifdef CONFIG_ADDR_MAP 141 extern void init_addr_map(void); 142 #endif 143 144 typedef enum { 145 IBAT0 = 0, IBAT1, IBAT2, IBAT3, 146 DBAT0, DBAT1, DBAT2, DBAT3, 147 #ifdef CONFIG_HIGH_BATS 148 IBAT4, IBAT5, IBAT6, IBAT7, 149 DBAT4, DBAT5, DBAT6, DBAT7 150 #endif 151 } ppc_bat_t; 152 153 extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); 154 extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); 155 extern void print_bats(void); 156 157 #endif /* __ASSEMBLY__ */ 158 159 #define BATU_VS 0x00000002 160 #define BATU_VP 0x00000001 161 #define BATU_INVALID 0x00000000 162 163 #define BATL_WRITETHROUGH 0x00000040 164 #define BATL_CACHEINHIBIT 0x00000020 165 #define BATL_MEMCOHERENCE 0x00000010 166 #define BATL_GUARDEDSTORAGE 0x00000008 167 #define BATL_NO_ACCESS 0x00000000 168 169 #define BATL_PP_MSK 0x00000003 170 #define BATL_PP_00 0x00000000 /* No access */ 171 #define BATL_PP_01 0x00000001 /* Read-only */ 172 #define BATL_PP_10 0x00000002 /* Read-write */ 173 #define BATL_PP_11 0x00000003 174 175 #define BATL_PP_NO_ACCESS BATL_PP_00 176 #define BATL_PP_RO BATL_PP_01 177 #define BATL_PP_RW BATL_PP_10 178 179 /* BAT Block size values */ 180 #define BATU_BL_128K 0x00000000 181 #define BATU_BL_256K 0x00000004 182 #define BATU_BL_512K 0x0000000c 183 #define BATU_BL_1M 0x0000001c 184 #define BATU_BL_2M 0x0000003c 185 #define BATU_BL_4M 0x0000007c 186 #define BATU_BL_8M 0x000000fc 187 #define BATU_BL_16M 0x000001fc 188 #define BATU_BL_32M 0x000003fc 189 #define BATU_BL_64M 0x000007fc 190 #define BATU_BL_128M 0x00000ffc 191 #define BATU_BL_256M 0x00001ffc 192 193 /* Block lengths for processors that support extended block length */ 194 #ifdef HID0_XBSEN 195 #define BATU_BL_512M 0x00003ffc 196 #define BATU_BL_1G 0x00007ffc 197 #define BATU_BL_2G 0x0000fffc 198 #define BATU_BL_4G 0x0001fffc 199 #define BATU_BL_MAX BATU_BL_4G 200 #else 201 #define BATU_BL_MAX BATU_BL_256M 202 #endif 203 204 /* BAT Access Protection */ 205 #define BPP_XX 0x00 /* No access */ 206 #define BPP_RX 0x01 /* Read only */ 207 #define BPP_RW 0x02 /* Read/write */ 208 209 /* Macros to get values from BATs, once data is in the BAT register format */ 210 #define BATU_VALID(x) (x & 0x3) 211 #define BATU_VADDR(x) (x & 0xfffe0000) 212 #define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ 213 | ((x & 0x0e00ULL) << 24) \ 214 | ((x & 0x04ULL) << 30))) 215 #define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17)) 216 217 /* bytes into BATU_BL */ 218 #define TO_BATU_BL(x) \ 219 (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4) 220 221 /* Used to set up SDR1 register */ 222 #define HASH_TABLE_SIZE_64K 0x00010000 223 #define HASH_TABLE_SIZE_128K 0x00020000 224 #define HASH_TABLE_SIZE_256K 0x00040000 225 #define HASH_TABLE_SIZE_512K 0x00080000 226 #define HASH_TABLE_SIZE_1M 0x00100000 227 #define HASH_TABLE_SIZE_2M 0x00200000 228 #define HASH_TABLE_SIZE_4M 0x00400000 229 #define HASH_TABLE_MASK_64K 0x000 230 #define HASH_TABLE_MASK_128K 0x001 231 #define HASH_TABLE_MASK_256K 0x003 232 #define HASH_TABLE_MASK_512K 0x007 233 #define HASH_TABLE_MASK_1M 0x00F 234 #define HASH_TABLE_MASK_2M 0x01F 235 #define HASH_TABLE_MASK_4M 0x03F 236 237 /* Control/status registers for the MPC8xx. 238 * A write operation to these registers causes serialized access. 239 * During software tablewalk, the registers used perform mask/shift-add 240 * operations when written/read. A TLB entry is created when the Mx_RPN 241 * is written, and the contents of several registers are used to 242 * create the entry. 243 */ 244 #define MI_CTR 784 /* Instruction TLB control register */ 245 #define MI_GPM 0x80000000 /* Set domain manager mode */ 246 #define MI_PPM 0x40000000 /* Set subpage protection */ 247 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 248 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 249 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 250 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ 251 #define MI_RESETVAL 0x00000000 /* Value of register at reset */ 252 253 /* These are the Ks and Kp from the PowerPC books. For proper operation, 254 * Ks = 0, Kp = 1. 255 */ 256 #define MI_AP 786 257 #define MI_Ks 0x80000000 /* Should not be set */ 258 #define MI_Kp 0x40000000 /* Should always be set */ 259 260 /* The effective page number register. When read, contains the information 261 * about the last instruction TLB miss. When MI_RPN is written, bits in 262 * this register are used to create the TLB entry. 263 */ 264 #define MI_EPN 787 265 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ 266 #define MI_EVALID 0x00000200 /* Entry is valid */ 267 #define MI_ASIDMASK 0x0000000f /* ASID match value */ 268 /* Reset value is undefined */ 269 270 /* A "level 1" or "segment" or whatever you want to call it register. 271 * For the instruction TLB, it contains bits that get loaded into the 272 * TLB entry when the MI_RPN is written. 273 */ 274 #define MI_TWC 789 275 #define MI_APG 0x000001e0 /* Access protection group (0) */ 276 #define MI_GUARDED 0x00000010 /* Guarded storage */ 277 #define MI_PSMASK 0x0000000c /* Mask of page size bits */ 278 #define MI_PS8MEG 0x0000000c /* 8M page size */ 279 #define MI_PS512K 0x00000004 /* 512K page size */ 280 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ 281 #define MI_SVALID 0x00000001 /* Segment entry is valid */ 282 /* Reset value is undefined */ 283 284 /* Real page number. Defined by the pte. Writing this register 285 * causes a TLB entry to be created for the instruction TLB, using 286 * additional information from the MI_EPN, and MI_TWC registers. 287 */ 288 #define MI_RPN 790 289 290 /* Define an RPN value for mapping kernel memory to large virtual 291 * pages for boot initialization. This has real page number of 0, 292 * large page size, shared page, cache enabled, and valid. 293 * Also mark all subpages valid and write access. 294 */ 295 #define MI_BOOTINIT 0x000001fd 296 297 #define MD_CTR 792 /* Data TLB control register */ 298 #define MD_GPM 0x80000000 /* Set domain manager mode */ 299 #define MD_PPM 0x40000000 /* Set subpage protection */ 300 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 301 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ 302 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 303 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ 304 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 305 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ 306 #define MD_RESETVAL 0x04000000 /* Value of register at reset */ 307 308 #define M_CASID 793 /* Address space ID (context) to match */ 309 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ 310 311 312 /* These are the Ks and Kp from the PowerPC books. For proper operation, 313 * Ks = 0, Kp = 1. 314 */ 315 #define MD_AP 794 316 #define MD_Ks 0x80000000 /* Should not be set */ 317 #define MD_Kp 0x40000000 /* Should always be set */ 318 319 /* The effective page number register. When read, contains the information 320 * about the last instruction TLB miss. When MD_RPN is written, bits in 321 * this register are used to create the TLB entry. 322 */ 323 #define MD_EPN 795 324 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ 325 #define MD_EVALID 0x00000200 /* Entry is valid */ 326 #define MD_ASIDMASK 0x0000000f /* ASID match value */ 327 /* Reset value is undefined */ 328 329 /* The pointer to the base address of the first level page table. 330 * During a software tablewalk, reading this register provides the address 331 * of the entry associated with MD_EPN. 332 */ 333 #define M_TWB 796 334 #define M_L1TB 0xfffff000 /* Level 1 table base address */ 335 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ 336 /* Reset value is undefined */ 337 338 /* A "level 1" or "segment" or whatever you want to call it register. 339 * For the data TLB, it contains bits that get loaded into the TLB entry 340 * when the MD_RPN is written. It is also provides the hardware assist 341 * for finding the PTE address during software tablewalk. 342 */ 343 #define MD_TWC 797 344 #define MD_L2TB 0xfffff000 /* Level 2 table base address */ 345 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ 346 #define MD_APG 0x000001e0 /* Access protection group (0) */ 347 #define MD_GUARDED 0x00000010 /* Guarded storage */ 348 #define MD_PSMASK 0x0000000c /* Mask of page size bits */ 349 #define MD_PS8MEG 0x0000000c /* 8M page size */ 350 #define MD_PS512K 0x00000004 /* 512K page size */ 351 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ 352 #define MD_WT 0x00000002 /* Use writethrough page attribute */ 353 #define MD_SVALID 0x00000001 /* Segment entry is valid */ 354 /* Reset value is undefined */ 355 356 357 /* Real page number. Defined by the pte. Writing this register 358 * causes a TLB entry to be created for the data TLB, using 359 * additional information from the MD_EPN, and MD_TWC registers. 360 */ 361 #define MD_RPN 798 362 363 /* This is a temporary storage register that could be used to save 364 * a processor working register during a tablewalk. 365 */ 366 #define M_TW 799 367 368 /* 369 * At present, all PowerPC 400-class processors share a similar TLB 370 * architecture. The instruction and data sides share a unified, 371 * 64-entry, fully-associative TLB which is maintained totally under 372 * software control. In addition, the instruction side has a 373 * hardware-managed, 4-entry, fully- associative TLB which serves as a 374 * first level to the shared TLB. These two TLBs are known as the UTLB 375 * and ITLB, respectively. 376 */ 377 378 #define PPC4XX_TLB_SIZE 64 379 380 /* 381 * TLB entries are defined by a "high" tag portion and a "low" data 382 * portion. On all architectures, the data portion is 32-bits. 383 * 384 * TLB entries are managed entirely under software control by reading, 385 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx 386 * instructions. 387 */ 388 389 /* 390 * FSL Book-E support 391 */ 392 393 #define MAS0_TLBSEL_MSK 0x30000000 394 #define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) 395 #define MAS0_ESEL_MSK 0x0FFF0000 396 #define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) 397 #define MAS0_NV(x) ((x) & 0x00000FFF) 398 399 #define MAS1_VALID 0x80000000 400 #define MAS1_IPROT 0x40000000 401 #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) 402 #define MAS1_TS 0x00001000 403 #define MAS1_TSIZE(x) (((x) << 7) & 0x00000F80) 404 #define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10)) 405 406 #define MAS2_EPN 0xFFFFF000 407 #define MAS2_X0 0x00000040 408 #define MAS2_X1 0x00000020 409 #define MAS2_W 0x00000010 410 #define MAS2_I 0x00000008 411 #define MAS2_M 0x00000004 412 #define MAS2_G 0x00000002 413 #define MAS2_E 0x00000001 414 415 #define MAS3_RPN 0xFFFFF000 416 #define MAS3_U0 0x00000200 417 #define MAS3_U1 0x00000100 418 #define MAS3_U2 0x00000080 419 #define MAS3_U3 0x00000040 420 #define MAS3_UX 0x00000020 421 #define MAS3_SX 0x00000010 422 #define MAS3_UW 0x00000008 423 #define MAS3_SW 0x00000004 424 #define MAS3_UR 0x00000002 425 #define MAS3_SR 0x00000001 426 427 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) 428 #define MAS4_TIDDSEL 0x000F0000 429 #define MAS4_TSIZED(x) MAS1_TSIZE(x) 430 #define MAS4_X0D 0x00000040 431 #define MAS4_X1D 0x00000020 432 #define MAS4_WD 0x00000010 433 #define MAS4_ID 0x00000008 434 #define MAS4_MD 0x00000004 435 #define MAS4_GD 0x00000002 436 #define MAS4_ED 0x00000001 437 438 #define MAS6_SPID0 0x3FFF0000 439 #define MAS6_SPID1 0x00007FFE 440 #define MAS6_SAS 0x00000001 441 #define MAS6_SPID MAS6_SPID0 442 443 #define MAS7_RPN 0xFFFFFFFF 444 445 #define FSL_BOOKE_MAS0(tlbsel,esel,nv) \ 446 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) 447 #define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \ 448 ((((v) << 31) & MAS1_VALID) |\ 449 (((iprot) << 30) & MAS1_IPROT) |\ 450 (MAS1_TID(tid)) |\ 451 (((ts) << 12) & MAS1_TS) |\ 452 (MAS1_TSIZE(tsize))) 453 #define FSL_BOOKE_MAS2(epn, wimge) \ 454 (((epn) & MAS3_RPN) | (wimge)) 455 #define FSL_BOOKE_MAS3(rpn, user, perms) \ 456 (((rpn) & MAS3_RPN) | (user) | (perms)) 457 #define FSL_BOOKE_MAS7(rpn) \ 458 (((u64)(rpn)) >> 32) 459 460 #define BOOKE_PAGESZ_1K 0 461 #define BOOKE_PAGESZ_2K 1 462 #define BOOKE_PAGESZ_4K 2 463 #define BOOKE_PAGESZ_8K 3 464 #define BOOKE_PAGESZ_16K 4 465 #define BOOKE_PAGESZ_32K 5 466 #define BOOKE_PAGESZ_64K 6 467 #define BOOKE_PAGESZ_128K 7 468 #define BOOKE_PAGESZ_256K 8 469 #define BOOKE_PAGESZ_512K 9 470 #define BOOKE_PAGESZ_1M 10 471 #define BOOKE_PAGESZ_2M 11 472 #define BOOKE_PAGESZ_4M 12 473 #define BOOKE_PAGESZ_8M 13 474 #define BOOKE_PAGESZ_16M 14 475 #define BOOKE_PAGESZ_32M 15 476 #define BOOKE_PAGESZ_64M 16 477 #define BOOKE_PAGESZ_128M 17 478 #define BOOKE_PAGESZ_256M 18 479 #define BOOKE_PAGESZ_512M 19 480 #define BOOKE_PAGESZ_1G 20 481 #define BOOKE_PAGESZ_2G 21 482 #define BOOKE_PAGESZ_4G 22 483 #define BOOKE_PAGESZ_8G 23 484 #define BOOKE_PAGESZ_16GB 24 485 #define BOOKE_PAGESZ_32GB 25 486 #define BOOKE_PAGESZ_64GB 26 487 #define BOOKE_PAGESZ_128GB 27 488 #define BOOKE_PAGESZ_256GB 28 489 #define BOOKE_PAGESZ_512GB 29 490 #define BOOKE_PAGESZ_1TB 30 491 #define BOOKE_PAGESZ_2TB 31 492 493 #define TLBIVAX_ALL 4 494 #define TLBIVAX_TLB0 0 495 #define TLBIVAX_TLB1 8 496 497 #ifdef CONFIG_E500 498 #ifndef __ASSEMBLY__ 499 extern void set_tlb(u8 tlb, u32 epn, u64 rpn, 500 u8 perms, u8 wimge, 501 u8 ts, u8 esel, u8 tsize, u8 iprot); 502 extern void disable_tlb(u8 esel); 503 extern void invalidate_tlb(u8 tlb); 504 extern void init_tlbs(void); 505 extern int find_tlb_idx(void *addr, u8 tlbsel); 506 extern void init_used_tlb_cams(void); 507 extern int find_free_tlbcam(void); 508 extern void print_tlbcam(void); 509 510 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); 511 extern void clear_ddr_tlbs(unsigned int memsize_in_meg); 512 513 enum tlb_map_type { 514 TLB_MAP_RAM, 515 TLB_MAP_IO, 516 }; 517 518 extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, 519 enum tlb_map_type map_type); 520 521 extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); 522 523 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ 524 { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ 525 .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ 526 .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ 527 .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ 528 .mas7 = FSL_BOOKE_MAS7(_rpn), } 529 530 struct fsl_e_tlb_entry { 531 u32 mas0; 532 u32 mas1; 533 u32 mas2; 534 u32 mas3; 535 u32 mas7; 536 }; 537 538 extern struct fsl_e_tlb_entry tlb_table[]; 539 extern int num_tlb_entries; 540 #endif 541 #endif 542 543 #ifdef CONFIG_E300 544 #define LAWAR_EN 0x80000000 545 #define LAWAR_SIZE 0x0000003F 546 547 #define LAWAR_TRGT_IF_PCI 0x00000000 548 #define LAWAR_TRGT_IF_PCI1 0x00000000 549 #define LAWAR_TRGT_IF_PCIX 0x00000000 550 #define LAWAR_TRGT_IF_PCI2 0x00100000 551 #define LAWAR_TRGT_IF_PCIE1 0x00200000 552 #define LAWAR_TRGT_IF_PCIE2 0x00100000 553 #define LAWAR_TRGT_IF_PCIE3 0x00300000 554 #define LAWAR_TRGT_IF_LBC 0x00400000 555 #define LAWAR_TRGT_IF_CCSR 0x00800000 556 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 557 #define LAWAR_TRGT_IF_RIO 0x00c00000 558 #define LAWAR_TRGT_IF_DDR 0x00f00000 559 #define LAWAR_TRGT_IF_DDR1 0x00f00000 560 #define LAWAR_TRGT_IF_DDR2 0x01600000 561 562 #define LAWAR_SIZE_BASE 0xa 563 #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) 564 #define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2) 565 #define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3) 566 #define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4) 567 #define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5) 568 #define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6) 569 #define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7) 570 #define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8) 571 #define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9) 572 #define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10) 573 #define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11) 574 #define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12) 575 #define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13) 576 #define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14) 577 #define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15) 578 #define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16) 579 #define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17) 580 #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) 581 #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) 582 #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) 583 #define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) 584 #define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) 585 #define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) 586 #define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) 587 #endif 588 589 #endif /* _PPC_MMU_H_ */ 590