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Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/mmc/
A Dzynq_sdhci.c63 [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
67 [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
211 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sdcardclk_set_phase()
267 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sampleclk_set_phase()
322 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sdcardclk_set_phase()
386 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sampleclk_set_phase()
517 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50, in arasan_dt_parse_clk_phases()
A Dxenon_sdhci.c283 (priv->timing == MMC_TIMING_UHS_DDR50) || in xenon_mmc_phy_set()
410 priv->timing = MMC_TIMING_UHS_DDR50; in xenon_sdhci_set_ios_post()
/u-boot/include/
A Dmmc.h372 #define MMC_TIMING_UHS_DDR50 7 macro

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