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Searched refs:MMC_TIMING_UHS_SDR50 (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/mmc/
A Dzynq_sdhci.c62 [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
66 [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
216 case MMC_TIMING_UHS_SDR50: in sdhci_zynqmp_sdcardclk_set_phase()
272 case MMC_TIMING_UHS_SDR50: in sdhci_zynqmp_sampleclk_set_phase()
327 case MMC_TIMING_UHS_SDR50: in sdhci_versal_sdcardclk_set_phase()
391 case MMC_TIMING_UHS_SDR50: in sdhci_versal_sampleclk_set_phase()
513 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50, in arasan_dt_parse_clk_phases()
A Dxenon_sdhci.c145 if ((priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_init()
281 (priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_set()
414 priv->timing = MMC_TIMING_UHS_SDR50; in xenon_sdhci_set_ios_post()
/u-boot/include/
A Dmmc.h370 #define MMC_TIMING_UHS_SDR50 5 macro

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