Home
last modified time | relevance | path

Searched refs:MMDC0 (Results 1 – 9 of 9) sorted by relevance

/u-boot/arch/arm/include/asm/arch-s32v234/
A Dmmdc.h9 #define MMDC0 0 macro
/u-boot/board/aristainetos/
A Dnt5cc256m16cp.cfg34 /* in DDR3, 64-bit mode, only MMDC0 is initiated */
/u-boot/board/freescale/s32v234evb/
A Dlpddr2.c106 case MMDC0: in config_mmdc()
/u-boot/board/softing/vining_2000/
A Dimximage.cfg105 /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
/u-boot/board/freescale/mx6sxsabreauto/
A Dimximage.cfg106 /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
/u-boot/board/freescale/mx6sxsabresd/
A Dimximage.cfg111 /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
/u-boot/board/seco/mx6quq7/
A Dmx6quq7-2g.cfg115 * in DDR3, 64-bit mode, only MMDC0 is init
/u-boot/board/freescale/mx6qarm2/
A Dimximage_mx6dl.cfg130 * MMDC channels: Both MMDC0, MMDC1
195 * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
/u-boot/arch/arm/dts/
A Dimx6qdl.dtsi1115 mmdc0: mmdc@21b0000 { /* MMDC0 */

Completed in 9 milliseconds