Searched refs:MMDC1 (Results 1 – 5 of 5) sorted by relevance
| /u-boot/arch/arm/include/asm/arch-s32v234/ |
| A D | mmdc.h | 10 #define MMDC1 1 macro
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 960 #define MMDC1(entry, value) do { \ macro
1445 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0); in mx6_ddr3_cfg()
1446 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1); in mx6_ddr3_cfg()
1460 MMDC1(mprddqby0dl, 0x33333333); in mx6_ddr3_cfg()
1461 MMDC1(mprddqby1dl, 0x33333333); in mx6_ddr3_cfg()
1462 MMDC1(mprddqby2dl, 0x33333333); in mx6_ddr3_cfg()
1463 MMDC1(mprddqby3dl, 0x33333333); in mx6_ddr3_cfg()
1470 MMDC1(mpodtctrl, val); in mx6_ddr3_cfg()
1476 MMDC1(mpmur0, val); in mx6_ddr3_cfg()
1516 MMDC1(mpzqhwctrl, val); in mx6_ddr3_cfg()
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| /u-boot/board/freescale/s32v234evb/ |
| A D | lpddr2.c | 117 case MMDC1: in config_mmdc()
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| /u-boot/board/freescale/mx6qarm2/ |
| A D | imximage_mx6dl.cfg | 130 * MMDC channels: Both MMDC0, MMDC1
195 * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
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| /u-boot/arch/arm/dts/ |
| A D | imx6qdl.dtsi | 1120 mmdc1: mmdc@21b4000 { /* MMDC1 */
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