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Searched refs:MMDC_MPZQHWCTRL (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/include/asm/arch-s32v234/
A Dmmdc.h42 #define MMDC_MPZQHWCTRL 0x800 macro
/u-boot/board/freescale/s32v234evb/
A Dlpddr2.c89 writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); in config_mmdc()
90 while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { in config_mmdc()
/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dimx-regs.h395 #define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) macro

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