Searched refs:MMDC_P0_BASE_ADDR (Results 1 – 7 of 7) sorted by relevance
| /u-boot/board/wandboard/ |
| A D | spl.c | 321 writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); in spl_dram_init_imx6qp_lpddr3()
323 writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); in spl_dram_init_imx6qp_lpddr3()
325 writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c); in spl_dram_init_imx6qp_lpddr3()
326 writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810); in spl_dram_init_imx6qp_lpddr3()
333 writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c); in spl_dram_init_imx6qp_lpddr3()
334 writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840); in spl_dram_init_imx6qp_lpddr3()
337 writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848); in spl_dram_init_imx6qp_lpddr3()
339 writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850); in spl_dram_init_imx6qp_lpddr3()
341 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); in spl_dram_init_imx6qp_lpddr3()
342 writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); in spl_dram_init_imx6qp_lpddr3()
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| /u-boot/arch/arm/mach-imx/ |
| A D | mmdc_size.c | 9 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
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| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 22 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in reset_read_data_fifos()
34 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in precharge_all()
55 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in force_delay_measurement()
109 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mmdc_do_write_level_calibration()
293 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mmdc_do_dqs_calibration()
1060 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mx6_lpddr2_cfg()
1290 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mx6_ddr3_cfg()
1652 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; in mmdc_read_calibration()
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| /u-boot/board/freescale/mx6ullevk/ |
| A D | plugin.S | 49 ldr r0, =MMDC_P0_BASE_ADDR
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| /u-boot/board/freescale/mx6sllevk/ |
| A D | plugin.S | 42 ldr r0, =MMDC_P0_BASE_ADDR
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| /u-boot/board/freescale/mx6qarm2/ |
| A D | imximage_mx6dl.cfg | 139 /* MMDC_P0_BASE_ADDR = 0x021b0000 */
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| /u-boot/arch/arm/include/asm/arch-mx6/ |
| A D | imx-regs.h | 267 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) macro
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