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Searched refs:MPHY_PGCR0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-uniphier/dram/
A Dumc-pxs2.c64 tmp = readl(phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
66 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
71 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
159 writel(0x07d81e37, phy_base + MPHY_PGCR0); in ddrphy_init()
A Dddrmphy-regs.h33 #define MPHY_PGCR0 (0x002 << MPHY_SHIFT) macro

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