Searched refs:MPLL (Results 1 – 9 of 9) sorted by relevance
/u-boot/arch/arm/mach-s5pc1xx/ |
A D | clock.c | 36 case MPLL: in s5pc100_get_pll_clk() 87 case MPLL: in s5pc110_get_pll_clk() 107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk() 206 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); in get_pclkd1() 236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
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/u-boot/arch/mips/mach-jz47xx/jz4780/ |
A D | pll.c | 358 MPLL, enumerator 414 (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) | in cpu_mux_select() 415 (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT); in cpu_mux_select() 457 { CPM_MSCCDR, MPLL, 30 }, in pll_init() 460 { CPM_GPUCDR, MPLL, 30 }, in pll_init() 463 { CPM_BCHCDR, MPLL, 30 }, in pll_init() 475 pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD); in pll_init() 479 cpu_mux_select(MPLL); in pll_init() 480 ddr_mux_select(MPLL); in pll_init()
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/u-boot/arch/arm/mach-exynos/ |
A D | clock.c | 196 case MPLL: in exynos4_get_pll_clk() 226 case MPLL: in exynos4x12_get_pll_clk() 257 case MPLL: in exynos5_get_pll_clk() 284 case MPLL: in exynos5_get_pll_clk() 315 case MPLL: in exynos542x_get_pll_clk() 668 sclk = get_pll_clk(MPLL); in exynos4_get_pwm_clk() 684 sclk = get_pll_clk(MPLL); in exynos4x12_get_pwm_clk() 714 sclk = get_pll_clk(MPLL); in exynos4_get_uart_clk() 760 sclk = get_pll_clk(MPLL); in exynos4x12_get_uart_clk() 796 sclk = get_pll_clk(MPLL); in exynos4_get_mmc_clk() [all …]
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/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
A D | clk.h | 12 #define MPLL 1 macro
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/u-boot/include/dt-bindings/clock/ |
A D | microchip,clock.h | 13 #define MPLL 2 macro
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/u-boot/arch/arm/mach-exynos/include/mach/ |
A D | clk.h | 11 #define MPLL 1 macro
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/u-boot/arch/mips/mach-pic32/ |
A D | cpu.c | 160 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); in soc_clk_dump()
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/u-boot/doc/device-tree-bindings/video/ |
A D | exynos-fb.txt | 55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
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/u-boot/drivers/clk/ |
A D | clk_pic32.c | 360 case MPLL: in pic32_get_rate()
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