Searched refs:MPU (Results 1 – 25 of 30) sorted by relevance
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| /u-boot/include/power/ |
| A D | tps65910.h | 11 #define MPU 0 macro
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| /u-boot/board/bosch/shc/ |
| A D | README | 82 MPU reference clock runs at 6 MHz
83 Setting MPU clock to 594 MHz
84 Enabling Spread Spectrum of 18 permille for MPU
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| /u-boot/board/siemens/pxm2/ |
| A D | board.c | 92 #define MPU 0 macro
100 if (module == MPU) in voltage_update()
159 if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || in spl_siemens_board_init()
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| /u-boot/arch/arm/mach-omap2/omap5/ |
| A D | Kconfig | 70 prompt "MPU Voltage Domain"
73 Select the Operating Performance Point(OPP) for the MPU voltage
79 This config option enables Normal OPP for MPU. This is the safest
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| /u-boot/drivers/power/pmic/ |
| A D | pmic_tps65910.c | 85 if (module == MPU) in tps65910_voltage_update()
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| /u-boot/doc/ |
| A D | README.arm-caches | 21 - Flush the buffer after the MPU writes the data and before the DMA is
30 - Invalidate the buffer after the DMA is complete and before the MPU reads
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| /u-boot/arch/arm/dts/ |
| A D | omap5-l4-abe.dtsi | 107 reg = <0x0 0xff>, /* MPU private access */
140 reg = <0x0 0xff>, /* MPU private access */
173 reg = <0x0 0xff>, /* MPU private access */
225 reg = <0x0 0x7f>, /* MPU private access */
268 reg = <0x0 0x7f>, /* MPU private access */
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| A D | omap4-l4-abe.dtsi | 107 reg = <0x0 0xff>, /* MPU private access */
140 reg = <0x0 0xff>, /* MPU private access */
173 reg = <0x0 0xff>, /* MPU private access */
241 reg = <0x0 0x7f>, /* MPU private access */
303 reg = <0x0 0x7f>, /* MPU private access */
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| A D | stm32mp157c-odyssey-som-u-boot.dtsi | 49 1 /*MPU*/
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| A D | stm32mp15xx-dhcor-u-boot.dtsi | 87 1 /*MPU*/
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| A D | stm32mp157a-dk1-u-boot.dtsi | 86 1 /*MPU*/
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| A D | stm32mp157c-ed1-u-boot.dtsi | 82 1 /*MPU*/
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| A D | omap4.dtsi | 99 * that are not memory mapped in the MPU view or for the MPU itself.
243 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
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| A D | stm32mp15xx-dhcom-u-boot.dtsi | 148 1 /*MPU*/
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| A D | dm816x.dtsi | 44 * that are not memory mapped in the MPU view or for the MPU itself.
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| A D | omap5.dtsi | 123 * that are not memory mapped in the MPU view or for the MPU itself.
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| A D | am33xx.dtsi | 156 * that are not memory mapped in the MPU view or for the MPU itself.
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| A D | omap3.dtsi | 56 * that are not memory mapped in the MPU view or for the MPU itself.
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| A D | exynos5420-peach-pit.dts | 212 /* MPU Clock source: LC => RCO */
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | st,stm32mp1.txt | 26 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
51 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
70 1 /*MPU*/
317 1 /*MPU*/
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| /u-boot/board/phytec/phycore_am335x_r2/ |
| A D | board.c | 213 if (tps65910_voltage_update(MPU, mpu_vdd)) in scale_vcores_generic()
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| /u-boot/arch/arm/mach-omap2/ |
| A D | Kconfig | 138 int "MPU CLK speed"
142 Defines the MPU clock speed (in MHz).
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| /u-boot/arch/arm/mach-at91/ |
| A D | Kconfig | 197 processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM
212 processor-based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM
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| /u-boot/arch/arm/mach-stm32mp/ |
| A D | Kconfig | 55 STMicroelectronics MPU with core ARMv7
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| /u-boot/board/vscom/baltos/ |
| A D | board.c | 209 if (tps65910_voltage_update(MPU, mpu_vdd)) in am33xx_spl_board_init()
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