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Searched refs:MSCC_QS_INJ_WR (Results 1 – 7 of 7) sorted by relevance

/u-boot/drivers/net/mscc_eswitch/
A Dmscc_xfer.c39 writel(ifh[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
42 writel(buff[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
46 writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
56 writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
A Dmscc_xfer.h12 MSCC_QS_INJ_WR, enumerator
A Dservalt_switch.c132 [MSCC_QS_INJ_WR] = 0x2c,
A Dserval_switch.c155 [MSCC_QS_INJ_WR] = 0x2c,
A Docelot_switch.c173 [MSCC_QS_INJ_WR] = 0x2c,
A Dluton_switch.c187 [MSCC_QS_INJ_WR] = 0x3c,
A Djr2_switch.c276 [MSCC_QS_INJ_WR] = 0x2c,

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