Searched refs:MTRR_PHYS_MASK_VALID (Results 1 – 7 of 7) sorted by relevance
52 valid = mask & MTRR_PHYS_MASK_VALID; in do_mtrr_list()56 mask & ~MTRR_PHYS_MASK_VALID, size); in do_mtrr_list()85 valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID; in do_mtrr_set()89 mask |= MTRR_PHYS_MASK_VALID; in do_mtrr_set()
66 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID); in set_var_mtrr()196 mask |= MTRR_PHYS_MASK_VALID; in mtrr_add_request()218 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) in get_free_var_mtrr()272 mask |= MTRR_PHYS_MASK_VALID; in mtrr_do_oper()274 mask &= ~MTRR_PHYS_MASK_VALID; in mtrr_do_oper()
114 or $MTRR_PHYS_MASK_VALID, %eax129 or $MTRR_PHYS_MASK_VALID, %eax143 or $MTRR_PHYS_MASK_VALID, %eax
89 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax143 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax154 movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
35 #define MTRR_PHYS_MASK_VALID (1 << 11) macro
55 mask | MTRR_PHYS_MASK_VALID); in quark_setup_mtrr()63 mask | MTRR_PHYS_MASK_VALID); in quark_setup_mtrr()
154 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); in dram_init()
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