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Searched refs:MTRR_VAR_PHYBASE (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/x86/cpu/quark/
A Dquark.c52 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), in quark_setup_mtrr()
60 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), in quark_setup_mtrr()
A Ddram.c151 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), in dram_init()
/u-boot/arch/x86/include/asm/arch-quark/
A Dquark.h69 #define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n)) macro

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