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Searched refs:MUX_M0 (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/cpu/armv8/hisilicon/
A Dpinmux.c25 writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */ in hi6220_uart_config()
26 writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */ in hi6220_uart_config()
33 writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */ in hi6220_uart_config()
34 writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */ in hi6220_uart_config()
35 writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */ in hi6220_uart_config()
36 writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */ in hi6220_uart_config()
47 writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */ in hi6220_uart_config()
48 writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */ in hi6220_uart_config()
142 writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */ in hi6220_mmc_config()
143 writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */ in hi6220_mmc_config()
[all …]
/u-boot/include/dt-bindings/pinctrl/
A Dhisi.h21 #define MUX_M0 0 macro
/u-boot/arch/arm/include/asm/arch-hi6220/
A Dpinmux.h14 #define MUX_M0 0 macro
/u-boot/arch/arm/dts/
A Dhikey960-pinctrl.dtsi39 0x044 MUX_M0 /* CSI0_PWD_N */
45 0x04c MUX_M0 /* CSI1_PWD_N */
67 0x080 MUX_M0 /* GPIO_034 */
93 0x11c MUX_M0 /* GPIO_073 */
94 0x120 MUX_M0 /* GPIO_074 */
161 0x0c8 MUX_M0 /* CAM0_RST */
167 0x124 MUX_M0 /* CAM1_RST */

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