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Searched refs:MUX_M1 (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/dts/
A Dhikey960-pinctrl.dtsi30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
51 0x058 MUX_M1 /* ISP_CLK0 */
52 0x064 MUX_M1 /* ISP_SCL0 */
53 0x068 MUX_M1 /* ISP_SDA0 */
59 0x05c MUX_M1 /* ISP_CLK1 */
60 0x06c MUX_M1 /* ISP_SCL1 */
61 0x070 MUX_M1 /* ISP_SDA1 */
73 0x02c MUX_M1 /* I2C3_SCL */
[all …]
/u-boot/arch/arm/cpu/armv8/hisilicon/
A Dpinmux.c57 writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */ in hi6220_uart_config()
58 writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */ in hi6220_uart_config()
59 writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */ in hi6220_uart_config()
60 writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */ in hi6220_uart_config()
73 writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */ in hi6220_uart_config()
74 writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */ in hi6220_uart_config()
75 writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */ in hi6220_uart_config()
76 writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */ in hi6220_uart_config()
88 writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */ in hi6220_uart_config()
89 writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */ in hi6220_uart_config()
/u-boot/arch/arm/include/asm/arch-hi6220/
A Dpinmux.h15 #define MUX_M1 1 macro
/u-boot/include/dt-bindings/pinctrl/
A Dhisi.h22 #define MUX_M1 1 macro

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