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Searched refs:MXC_CCM_CBCMR_DDR_CLK_SEL_RD (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/mx5/
A Dclock.c452 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in get_ddr_clk()
810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in config_ddr_clk()
/u-boot/arch/arm/include/asm/arch-mx5/
A Dcrm_regs.h258 #define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) macro

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