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Searched refs:MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/mx5/
A Dclock.c274 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) { in get_periph_clk()
780 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD( in config_periph_clk()
/u-boot/arch/arm/include/asm/arch-mx5/
A Dcrm_regs.h254 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) macro

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