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Searched refs:MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/board/compulab/cm_fx6/
A Dcm_fx6.c86 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); in cm_fx6_enable_hdmi()
117 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); in cm_fx6_setup_display()
/u-boot/arch/arm/include/asm/arch-mx6/
A Dcrm_regs.h809 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) macro

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