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Searched refs:MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/include/asm/arch-mx6/
A Dcrm_regs.h808 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 macro
809 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
/u-boot/drivers/video/imx/
A Dipu_common.c217 .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,

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