Searched refs:MXC_CCM_CCGR3_LDB_DI0_MASK (Results 1 – 17 of 17) sorted by relevance
133 reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()148 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()
220 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_b850v3()266 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_bx50v3()
151 reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); in setup_display()
236 clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display()249 setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display()
397 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_clock()
253 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; in setup_display()
292 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display()
415 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display()
475 MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display()
421 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; in setup_display()
446 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; in setup_display()
511 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()
604 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()
718 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()
820 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) macro
646 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK | in setup_display()
469 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()
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