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Searched refs:MXC_CCM_CCSR_PLL2_SW_CLK_SEL (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-imx/mx5/
A Dclock.c666 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL, in config_pll_clk()
672 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL, in config_pll_clk()
/u-boot/arch/arm/include/asm/arch-mx5/
A Dcrm_regs.h103 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) macro
/u-boot/arch/arm/include/asm/arch-mx6/
A Dcrm_regs.h234 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) macro

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