Searched refs:MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (Results 1 – 19 of 19) sorted by relevance
143 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
217 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_b850v3()263 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_bx50v3()
168 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
411 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) in setup_display_clock()
270 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
342 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
180 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in enable_lvds()
289 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
412 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
245 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
487 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
438 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
463 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
528 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
621 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
735 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
500 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 macro
661 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET | in setup_display()
486 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
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