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Searched refs:MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (Results 1 – 19 of 19) sorted by relevance

/u-boot/board/tbs/tbs2910/
A Dtbs2910.c143 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/ge/bx50v3/
A Dbx50v3.c217 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_b850v3()
263 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_bx50v3()
/u-boot/board/engicam/imx6q/
A Dimx6q.c168 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/kosagi/novena/
A Dvideo.c411 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) in setup_display_clock()
/u-boot/board/technexion/pico-imx6/
A Dpico-imx6.c270 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/wandboard/
A Dwandboard.c342 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/aristainetos/
A Daristainetos.c180 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in enable_lvds()
/u-boot/board/ge/b1x5v2/
A Db1x5v2.c289 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
/u-boot/board/advantech/dms-ba16/
A Ddms-ba16.c412 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
/u-boot/board/solidrun/mx6cuboxi/
A Dmx6cuboxi.c245 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/embest/mx6boards/
A Dmx6boards.c487 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
/u-boot/board/freescale/mx6sabresd/
A Dmx6sabresd.c438 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/freescale/mx6sabreauto/
A Dmx6sabreauto.c463 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/toradex/colibri_imx6/
A Dcolibri_imx6.c528 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/toradex/apalis_imx6/
A Dapalis_imx6.c621 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/board/boundary/nitrogen6x/
A Dnitrogen6x.c735 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
/u-boot/arch/arm/include/asm/arch-mx6/
A Dcrm_regs.h500 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 macro
/u-boot/board/congatec/cgtqmx6eval/
A Dcgtqmx6eval.c661 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET | in setup_display()
/u-boot/board/gateworks/gw_ventana/
A Dgw_ventana.c486 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()

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