Searched refs:MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (Results 1 – 16 of 16) sorted by relevance
209 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_b850v3()257 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_bx50v3()
163 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
405 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_clock()
265 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; in setup_display()
175 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in enable_lvds()
282 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display()
404 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display()
483 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display()
433 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; in setup_display()
458 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; in setup_display()
523 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
616 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
730 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
345 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) macro
657 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | in setup_display()
481 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
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