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Searched refs:NDTR0CS0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/mtd/nand/raw/
A Dpxa3xx_nand.c51 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ macro
467 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_timing()
506 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_sdr_timing()
1084 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc()
1145 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc_extended()
1503 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); in pxa3xx_nand_detect_config()
/u-boot/arch/arm/include/asm/arch-pxa/
A Dpxa-regs.h2335 #define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ macro

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