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Searched refs:NUM_CHANNELS (Results 1 – 5 of 5) sorted by relevance

/u-boot/arch/x86/include/asm/arch-quark/
A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
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/u-boot/drivers/pwm/
A Dsandbox_pwm.c14 NUM_CHANNELS = 3, enumerator
33 struct sandbox_pwm_chan chan[NUM_CHANNELS];
42 if (channel >= NUM_CHANNELS) in sandbox_pwm_get_config()
59 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_config()
74 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_enable()
88 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_invert()
/u-boot/arch/x86/cpu/quark/
A Dsmc.c279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
303 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
934 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
970 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1006 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1058 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1356 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1384 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1445 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
1591 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_level()
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A Dmrc_util.c1359 for (channel = 0; channel < NUM_CHANNELS; channel++) { in clear_pointers()
1456 for (channel = 0; channel < NUM_CHANNELS; channel++) { in print_timings()
/u-boot/drivers/adc/
A Dmeson-saradc.c164 #define NUM_CHANNELS 8 macro
629 if (channel < 0 || channel >= NUM_CHANNELS) { in meson_saradc_start_channel()
712 uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0); in meson_saradc_of_to_plat()

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