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Searched refs:NV_PA_PMC_BASE (Results 1 – 13 of 13) sorted by relevance

/u-boot/arch/arm/mach-tegra/
A Dpmc.c26 saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); in tegra_pmc_detect_tz_only()
33 writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0); in tegra_pmc_detect_tz_only()
34 value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); in tegra_pmc_detect_tz_only()
42 writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0); in tegra_pmc_detect_tz_only()
67 return readl(NV_PA_PMC_BASE + offset); in tegra_pmc_readl()
85 writel(value, NV_PA_PMC_BASE + offset); in tegra_pmc_writel()
A Dsys_info.c15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in get_reset_cause()
A Dap.c154 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in init_pmc_scratch()
A Dboard2.c74 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_det_init()
/u-boot/arch/arm/include/asm/arch-tegra/
A Dtegra.h36 #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) macro
38 #define NV_PA_PMC_BASE 0xc360000 macro
111 #define PRM_RSTCTRL NV_PA_PMC_BASE
/u-boot/arch/arm/mach-tegra/tegra124/
A Dcpu.c25 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()
153 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in tegra124_init_clocks()
235 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_partition_powered()
245 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in unpower_partition()
284 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_partition()
324 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in start_cpu()
/u-boot/arch/arm/mach-tegra/tegra114/
A Dcpu.c22 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()
190 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_partition_powered()
200 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_clamp_enabled()
210 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_partition()
/u-boot/arch/arm/mach-tegra/tegra20/
A Dcpu.c15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()
A Dclock.c651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
A Dwarmboot_avp.c26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in wb_start()
A Dwarmboot.c128 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in warmboot_save_sdram_params()
/u-boot/arch/arm/mach-tegra/tegra30/
A Dclock.c680 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
682 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
684 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
686 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
688 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
690 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
A Dcpu.c52 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()

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