1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the TechNexion TAO-3530 SOM 4 * equipped on Thunder baseboard. 5 * 6 * Edward Lin <linuxfae@technexion.com> 7 * Tapani Utriainen <linuxfae@technexion.com> 8 * 9 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 19 #include <asm/arch/cpu.h> /* get chip and board defs */ 20 #include <asm/arch/omap.h> 21 22 /* Clock Defines */ 23 #define V_OSCK 26000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK >> 1) 25 26 #define CONFIG_CMDLINE_TAG 27 #define CONFIG_SETUP_MEMORY_TAGS 28 #define CONFIG_INITRD_TAG 29 #define CONFIG_REVISION_TAG 30 31 /* 32 * Size of malloc() pool 33 */ 34 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 35 36 /* 37 * Hardware drivers 38 */ 39 40 /* 41 * NS16550 Configuration 42 */ 43 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 44 45 #define CONFIG_SYS_NS16550_SERIAL 46 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 47 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 48 49 /* 50 * select serial console configuration 51 */ 52 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 53 54 /* commands to include */ 55 56 #define CONFIG_SYS_I2C 57 #define CONFIG_I2C_MULTI_BUS 58 59 /* 60 * TWL4030 61 */ 62 63 /* 64 * Board NAND Info. 65 */ 66 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 67 /* to access nand at */ 68 /* CS0 */ 69 70 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 71 /* devices */ 72 /* Environment information */ 73 74 #define CONFIG_EXTRA_ENV_SETTINGS \ 75 "loadaddr=0x82000000\0" \ 76 "console=ttyO2,115200n8\0" \ 77 "mpurate=600\0" \ 78 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 79 "tv_mode=omapfb.mode=tv:ntsc\0" \ 80 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 81 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 82 "extra_options= \0" \ 83 "mmcdev=0\0" \ 84 "mmcroot=/dev/mmcblk0p2 rw\0" \ 85 "mmcrootfstype=ext3 rootwait\0" \ 86 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 87 "nandrootfstype=ubifs\0" \ 88 "mmcargs=setenv bootargs console=${console} " \ 89 "mpurate=${mpurate} " \ 90 "${video_mode} " \ 91 "root=${mmcroot} " \ 92 "rootfstype=${mmcrootfstype} " \ 93 "${extra_options}\0" \ 94 "nandargs=setenv bootargs console=${console} " \ 95 "mpurate=${mpurate} " \ 96 "${video_mode} " \ 97 "${network_setting} " \ 98 "root=${nandroot} " \ 99 "rootfstype=${nandrootfstype} "\ 100 "${extra_options}\0" \ 101 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 102 "bootscript=echo Running bootscript from mmc ...; " \ 103 "source ${loadaddr}\0" \ 104 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 105 "mmcboot=echo Booting from mmc ...; " \ 106 "run mmcargs; " \ 107 "bootm ${loadaddr}\0" \ 108 "nandboot=echo Booting from nand ...; " \ 109 "run nandargs; " \ 110 "nand read ${loadaddr} 280000 400000; " \ 111 "bootm ${loadaddr}\0" \ 112 113 #define CONFIG_BOOTCOMMAND \ 114 "mmc dev ${mmcdev}; if mmc rescan; then " \ 115 "if run loadbootscript; then " \ 116 "run bootscript; " \ 117 "else " \ 118 "if run loaduimage; then " \ 119 "run mmcboot; " \ 120 "else run nandboot; " \ 121 "fi; " \ 122 "fi; " \ 123 "else run nandboot; fi" 124 125 /* 126 * Miscellaneous configurable options 127 */ 128 129 /* turn on command-line edit/hist/auto */ 130 131 /* defaults */ 132 133 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 134 /* load address */ 135 136 /* 137 * OMAP3 has 12 GP timers, they can be driven by the system clock 138 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 139 * This rate is divided by a local divisor. 140 */ 141 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 142 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 143 144 /* 145 * Physical Memory Map 146 */ 147 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 148 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 149 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 150 151 /* 152 * FLASH and environment organization 153 */ 154 155 /* **** PISMO SUPPORT *** */ 156 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 157 #define CONFIG_SYS_FLASH_BASE NAND_BASE 158 159 /* Monitor at start of flash */ 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 161 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 162 163 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 164 165 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 166 167 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 168 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 169 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 170 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 171 CONFIG_SYS_INIT_RAM_SIZE - \ 172 GENERATED_GBL_DATA_SIZE) 173 174 /* 175 * USB 176 * 177 * Currently only EHCI is enabled, the MUSB OTG controller 178 * is not enabled. 179 */ 180 181 /* USB EHCI */ 182 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 183 184 /* Defines for SPL */ 185 186 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 187 188 /* NAND boot config */ 189 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 190 #define CONFIG_SYS_NAND_PAGE_COUNT 64 191 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 192 #define CONFIG_SYS_NAND_OOBSIZE 64 193 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 194 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 195 /* 196 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 197 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 198 */ 199 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 200 10, 11, 12, 13 } 201 #define CONFIG_SYS_NAND_ECCSIZE 512 202 #define CONFIG_SYS_NAND_ECCBYTES 3 203 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 204 205 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 206 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 207 208 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 209 CONFIG_SPL_TEXT_BASE) 210 211 /* 212 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 213 * older x-loader implementations. And move the BSS area so that it 214 * doesn't overlap with TEXT_BASE. 215 */ 216 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 217 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 218 219 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 220 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 221 222 #endif /* __CONFIG_H */ 223