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Searched refs:OSC_HZ (Results 1 – 22 of 22) sorted by relevance

/u-boot/drivers/clk/rockchip/
A Dclk_rk3036.c38 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
40 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
41 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
56 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
198 return OSC_HZ; in rkclk_pll_get_rate()
239 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; in rockchip_mmc_get_clk()
255 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
A Dclk_rk3368.c40 #define OSC_HZ (24 * 1000 * 1000) macro
49 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
50 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
77 return OSC_HZ; in rkclk_pll_get_rate()
98 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
187 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
440 return DIV_TO_RATE(OSC_HZ, div); in rk3368_saradc_get_clk()
447 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
A Dclk_rk3128.c35 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
49 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
82 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config()
266 return OSC_HZ; in rkclk_pll_get_rate()
307 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; in rockchip_mmc_get_clk()
323 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
403 return DIV_TO_RATE(OSC_HZ, div); in rk3128_saradc_get_clk()
410 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
A Dclk_rk322x.c36 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
38 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
39 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
54 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
200 return OSC_HZ; in rkclk_pll_get_rate()
242 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; in rockchip_mmc_get_clk()
293 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
A Dclk_rv1108.c39 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
41 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
42 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
78 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
143 freq = OSC_HZ; in rkclk_pll_get_rate()
203 return DIV_TO_RATE(OSC_HZ, div); in rv1108_saradc_get_clk()
210 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
504 mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2; in rv1108_mmc_get_clk()
528 pll_rate = OSC_HZ; in rv1108_mmc_set_clk()
A Dclk_rk3288.c141 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
142 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
157 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
236 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; in pll_para_config()
561 return OSC_HZ; in rkclk_pll_get_rate()
607 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; in rockchip_mmc_get_clk()
622 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
733 return DIV_TO_RATE(OSC_HZ, div); in rockchip_saradc_get_clk()
740 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
A Dclk_rk3328.c39 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
246 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
468 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3328_mmc_get_clk()
497 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3328_mmc_set_clk()
542 return DIV_TO_RATE(OSC_HZ, div); in rk3328_saradc_get_clk()
549 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_saradc_set_clk()
566 return DIV_TO_RATE(OSC_HZ, div); in rk3328_spi_get_clk()
A Dclk_rk3188.c79 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
80 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
96 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
247 return OSC_HZ; in rkclk_pll_get_rate()
A Dclk_pll.c39 OSC_HZ = 24 * 1000000, enumerator
264 return OSC_HZ; in rk3036_pll_get_rate()
284 u64 frac_rate = OSC_HZ * (u64)frac; in rk3036_pll_get_rate()
A Dclk_rk3308.c263 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3308_mmc_get_clk()
293 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3308_mmc_set_clk()
319 return DIV_TO_RATE(OSC_HZ, div); in rk3308_saradc_get_clk()
328 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_saradc_set_clk()
347 return DIV_TO_RATE(OSC_HZ, div); in rk3308_tsadc_get_clk()
356 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_tsadc_set_clk()
466 parent = OSC_HZ; in rk3308_vop_get_clk()
526 if (best_rate != hz && hz == OSC_HZ) { in rk3308_vop_set_clk()
A Dclk_px30.c101 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto()
220 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
273 return OSC_HZ; in rkclk_pll_get_rate()
536 return DIV_TO_RATE(OSC_HZ, div) / 2; in px30_mmc_get_clk()
567 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in px30_mmc_set_clk()
645 return DIV_TO_RATE(OSC_HZ, div); in px30_saradc_get_clk()
653 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_saradc_set_clk()
671 return DIV_TO_RATE(OSC_HZ, div); in px30_tsadc_get_clk()
679 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_tsadc_set_clk()
A Dclk_rk3399.c54 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
328 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
370 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config()
748 return DIV_TO_RATE(OSC_HZ, div); in rk3399_mmc_get_clk()
768 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
896 return DIV_TO_RATE(OSC_HZ, div); in rk3399_saradc_get_clk()
903 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3399_saradc_set_clk()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dcru_rk3328.h47 #define OSC_HZ (24 * MHz) macro
A Dcru_rk3188.h8 #define OSC_HZ (24 * 1000 * 1000) macro
A Dcru_rk3399.h68 #define OSC_HZ (24*MHz) macro
A Dcru_rk3036.h8 #define OSC_HZ (24 * 1000 * 1000) macro
A Dcru_rk3128.h14 #define OSC_HZ (24 * MHz) macro
A Dcru_rk322x.h9 #define OSC_HZ (24 * MHz) macro
A Dcru_rk3288.h11 #define OSC_HZ (24 * 1000 * 1000) macro
A Dcru_rv1108.h13 #define OSC_HZ (24 * 1000 * 1000) macro
A Dcru_px30.h10 #define OSC_HZ (24 * MHz) macro
/u-boot/arch/arm/include/asm/arch-rk3308/
A Dcru_rk3308.h9 #define OSC_HZ (24 * MHz) macro

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