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Searched refs:OTHER_ADDR_OFFSET (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/video/nexell/soc/
A Ds5pxx18_soc_hdmi.h404 #define HDMI_CEC_TX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000000)
405 #define HDMI_CEC_TX_STATUS_1 (OTHER_ADDR_OFFSET + 0x00000004)
406 #define HDMI_CEC_RX_STATUS_0 (OTHER_ADDR_OFFSET + 0x00000008)
407 #define HDMI_CEC_RX_STATUS_1 (OTHER_ADDR_OFFSET + 0x0000000C)
408 #define HDMI_CEC_INTR_MASK (OTHER_ADDR_OFFSET + 0x00000010)
409 #define HDMI_CEC_INTR_CLEAR (OTHER_ADDR_OFFSET + 0x00000014)
410 #define HDMI_CEC_LOGIC_ADDR (OTHER_ADDR_OFFSET + 0x00000020)
411 #define HDMI_CEC_DIVISOR_0 (OTHER_ADDR_OFFSET + 0x00000030)
412 #define HDMI_CEC_DIVISOR_1 (OTHER_ADDR_OFFSET + 0x00000034)
413 #define HDMI_CEC_DIVISOR_2 (OTHER_ADDR_OFFSET + 0x00000038)
[all …]
A Ds5pxx18_soc_disptop.h21 #define OTHER_ADDR_OFFSET \ macro
24 #define PHY_BASEADDR_DISPLAYTOP_MODULE_OFFSET (OTHER_ADDR_OFFSET + 0x001000)
26 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x002000)
28 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x003000)
30 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x004000)
33 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x00a000)
300 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x006000)
302 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x007000)
304 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x005000)
306 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x008000)
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