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Searched refs:OUT_CLK_DIVISOR_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-tegra/
A Dclock.c177 value &= ~OUT_CLK_DIVISOR_MASK; in clock_ll_set_source_divisor()
317 int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT; in clock_get_periph_rate()
414 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK, in adjust_periph_pll()
/u-boot/arch/arm/include/asm/arch-tegra/
A Dclk_rst.h321 #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) macro

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