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/u-boot/lib/
A Dsha1.c110 P (A, B, C, D, E, W[0]); in sha1_process()
111 P (E, A, B, C, D, W[1]); in sha1_process()
112 P (D, E, A, B, C, W[2]); in sha1_process()
113 P (C, D, E, A, B, W[3]); in sha1_process()
114 P (B, C, D, E, A, W[4]); in sha1_process()
115 P (A, B, C, D, E, W[5]); in sha1_process()
116 P (E, A, B, C, D, W[6]); in sha1_process()
117 P (D, E, A, B, C, W[7]); in sha1_process()
118 P (C, D, E, A, B, W[8]); in sha1_process()
119 P (B, C, D, E, A, W[9]); in sha1_process()
[all …]
A Dsha256.c99 #define P(a,b,c,d,e,f,g,h,x,K) { \ in sha256_process() macro
114 P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); in sha256_process()
115 P(H, A, B, C, D, E, F, G, W[1], 0x71374491); in sha256_process()
116 P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); in sha256_process()
117 P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); in sha256_process()
118 P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); in sha256_process()
119 P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); in sha256_process()
120 P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); in sha256_process()
121 P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); in sha256_process()
122 P(A, B, C, D, E, F, G, H, W[8], 0xD807AA98); in sha256_process()
[all …]
/u-boot/doc/chromium/devkeys/
A Dkernel.keyblock3 …P{� f��~`�ܿ�\��L��JY0���!)P�v�/Zgj�k@'��_��k��}ː�<�y�G�X�?���g�"�p36�\��N�$ [�M��j1�^_�X��)…
5 گ��\F���l�N��k��K���6��Ց�~����ܾ���(/��kH�Q�m���li��(P~t��j �k��ޣ_#�*D��$63�~�������…
/u-boot/arch/arm/dts/
A Dtegra186-p2771-0000-000.dts10 cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>;
11 power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
A Dtegra186-p2771-0000-500.dts10 cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
11 power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
A Dstm32mp157c-odyssey-som-u-boot.dtsi100 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
109 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
118 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
A Domap4-l4.dtsi54 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
154 /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
332 /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
473 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
494 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
588 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
627 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
665 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
733 /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
2002 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
[all …]
A Domap4-l4-abe.dtsi97 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
130 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
163 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
195 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
231 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
264 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
290 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
324 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
354 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
384 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
[all …]
A Dstm32mp15xx-dhcor-u-boot.dtsi138 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
147 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
156 /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
A Domap5-l4-abe.dtsi97 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
130 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
163 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
215 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
255 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
289 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
320 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
351 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
381 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
440 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
A Domap5-l4.dtsi183 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
231 /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
362 /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
605 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
644 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
1048 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1074 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1101 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1128 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1155 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
[all …]
A Dam33xx-l4.dtsi880 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
911 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
944 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
965 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
996 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1026 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1059 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1086 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1111 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1137 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
[all …]
A Dstm32mp157a-dk1-u-boot.dtsi137 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
146 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
155 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
A Dstm32mp157c-ed1-u-boot.dtsi133 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
142 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
151 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
A Dtegra20-trimslice.dts59 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
60 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
A Dstm32mp15xx-dhcom-u-boot.dtsi199 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
208 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
217 /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
A Dtegra186-p2771-0000.dtsi53 wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
/u-boot/common/
A Ddlmalloc.c881 #define check_free_chunk(P) do_check_free_chunk(P) argument
882 #define check_inuse_chunk(P) do_check_inuse_chunk(P) argument
883 #define check_chunk(P) do_check_chunk(P) argument
884 #define check_malloced_chunk(P,N) do_check_malloced_chunk(P,N) argument
886 #define check_free_chunk(P) argument
887 #define check_inuse_chunk(P) argument
888 #define check_chunk(P) argument
889 #define check_malloced_chunk(P,N) argument
910 #define frontlink(P, S, IDX, BK, FD) \ argument
918 P->bk = BK; \
[all …]
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_write_leveling.c123 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
150 [P], 1); in ddr3_write_leveling_hw()
348 [pup_num][P] + in ddr3_wl_supplement()
353 [P] = phase; in ddr3_wl_supplement()
369 [P]; in ddr3_wl_supplement()
386 [P] = phase; in ddr3_wl_supplement()
546 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
556 dram_info->wl_val[cs][pup][P] = in ddr3_write_leveling_hw_reg_dimm()
586 [P], 1); in ddr3_write_leveling_hw_reg_dimm()
1270 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
[all …]
A Dddr3_read_leveling.c112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
291 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
1129 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
/u-boot/scripts/
A Dget_maintainer.pl16 my $P = $0;
277 print("${P} ${V}\n");
317 die "$P: Please select at least 1 email option\n";
321 die "$P: The current directory does not appear to be "
336 or die "$P: Can't open MAINTAINERS file '$file': $!\n";
425 or warn "$P: Can't open .mailmap: $!\n";
503 die "$P: file '${file}' not found\n";
512 or die "$P: Can't open $file: $!\n";
532 or die "$P: Can't open $file: $!\n";
977 usage: $P [options] patchfile
[all …]
/u-boot/arch/x86/include/asm/acpi/
A Dirq_helper.h38 Name(prefix_ ## func_ ## P, Package() \
104 Return (prefix_ ## func_ ## P) \
/u-boot/arch/arm/mach-sunxi/
A Dclock_sun4i.c81 #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ argument
86 (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
/u-boot/doc/device-tree-bindings/clock/
A Dst,stm32mp1.txt110 BIT(0) => output P : DIVPEN
368 /* VCO = 1300.0 MHz => P = 650 (CPU) */
377 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
387 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
396 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
/u-boot/doc/SPI/
A DREADME.ftssp010_spi_test41 108000f0: e28d0048 e28d5034 e1a0100e e885000f H...4P..........

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