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Searched refs:PAD_CFG0_LOGICAL_RESET_DEEP (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/pinctrl/intel/
A Dpinctrl_apl.c22 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
/u-boot/arch/x86/dts/
A Dchromebook_coral.dts630 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
634 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
638 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
643 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
646 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
649 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
660 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
/u-boot/arch/x86/include/asm/
A Dintel_pinctrl_defs.h50 #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) macro

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