| /u-boot/arch/arm/include/asm/mach-imx/ |
| A D | iomux-v3.h | 105 #define PAD_CTL_PUE (0x1 << 6) macro
131 #define PAD_CTL_PUE (0x1 << 4) macro
145 #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
147 #define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
148 #define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) macro
206 #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
208 #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
210 #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) macro
223 #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) macro
225 #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
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| /u-boot/board/liebherr/display5/ |
| A D | common.h | 10 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
14 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
18 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /u-boot/board/gateworks/gw_ventana/ |
| A D | common.h | 18 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
22 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 #define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /u-boot/arch/arm/include/asm/arch-mx7ulp/ |
| A D | iomux.h | 86 #define PAD_CTL_PUE (1 << 1) macro
87 #define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE)
88 #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
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| /u-boot/board/ccv/xpress/ |
| A D | xpress.c | 34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
42 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /u-boot/board/freescale/mx6ul_14x14_evk/ |
| A D | mx6ul_14x14_evk.c | 38 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
42 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
54 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
128 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /u-boot/board/freescale/mx6sxsabresd/ |
| A D | mx6sxsabresd.c | 36 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
57 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
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| /u-boot/board/grinn/liteboard/ |
| A D | board.c | 35 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
47 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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| /u-boot/board/technexion/pico-imx6ul/ |
| A D | pico-imx6ul.c | 31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
42 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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| /u-boot/board/kosagi/novena/ |
| A D | novena_spl.c | 33 (PAD_CTL_PKE | PAD_CTL_PUE | \
38 (PAD_CTL_PKE | PAD_CTL_PUE | \
43 (PAD_CTL_PKE | PAD_CTL_PUE | \
48 (PAD_CTL_PKE | PAD_CTL_PUE | \
52 (PAD_CTL_PKE | PAD_CTL_PUE | \
61 (PAD_CTL_PKE | PAD_CTL_PUE | \
67 (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /u-boot/board/phytec/phycore_imx8mp/ |
| A D | spl.c | 36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /u-boot/board/udoo/neo/ |
| A D | neo.c | 48 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
52 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
61 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
68 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
71 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
74 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /u-boot/board/freescale/mx6sxsabreauto/ |
| A D | mx6sxsabreauto.c | 36 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
50 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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| /u-boot/board/tqc/tqma6/ |
| A D | tqma6_wru4.c | 41 PAD_CTL_PUE | \
143 PAD_CTL_PUE | \
194 PAD_CTL_PUE | \
203 PAD_CTL_PUE | \
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| /u-boot/board/toradex/verdin-imx8mm/ |
| A D | spl.c | 78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /u-boot/board/phytec/pcl063/ |
| A D | pcl063.c | 33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
95 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
99 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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| /u-boot/board/freescale/imx8mq_evk/ |
| A D | spl.c | 45 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
81 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
83 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
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| A D | imx8mq_evk.c | 34 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
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| /u-boot/board/compulab/cl-som-imx7/ |
| A D | mux.c | 23 PAD_CTL_HYS | PAD_CTL_PUE | \
56 #define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \
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| /u-boot/board/google/imx8mq_phanbell/ |
| A D | spl.c | 57 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
59 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
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| A D | imx8mq_phanbell.c | 29 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
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| /u-boot/board/variscite/dart_6ul/ |
| A D | spl.c | 17 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
113 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /u-boot/board/technexion/pico-imx8mq/ |
| A D | spl.c | 116 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
118 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
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| /u-boot/board/freescale/imx8mn_evk/ |
| A D | spl.c | 66 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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| /u-boot/board/beacon/imx8mn/ |
| A D | spl.c | 72 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|