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Searched refs:PAD_CTL_PUS_100K_UP (Results 1 – 25 of 66) sorted by relevance

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/u-boot/board/barco/platinum/
A Dplatinum.h27 #define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
31 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 #define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/u-boot/board/tqc/tqma6/
A Dtqma6_mba6.c35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
44 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
47 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
50 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
53 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
A Dtqma6.c43 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
46 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
49 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
52 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
A Dtqma6_wru4.c40 PAD_CTL_PUS_100K_UP | \
142 PAD_CTL_PUS_100K_UP | \
193 PAD_CTL_PUS_100K_UP | \
202 PAD_CTL_PUS_100K_UP | \
/u-boot/board/liebherr/display5/
A Dcommon.h11 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
31 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
/u-boot/board/gateworks/gw_ventana/
A Dcommon.h19 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/u-boot/arch/arm/include/asm/arch-mx25/
A Diomux-mx25.h21 #define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
22 #define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
165 MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
173 MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
267 MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
342 MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
346 MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
412 MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
417 MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
422 MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
[all …]
/u-boot/board/freescale/mx6ul_14x14_evk/
A Dmx6ul_14x14_evk.c39 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
43 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
54 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/u-boot/board/grinn/liteboard/
A Dboard.c36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
47 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/u-boot/board/phytec/pcl063/
A Dpcl063.c34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
95 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
99 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/u-boot/board/technexion/pico-imx6ul/
A Dpico-imx6ul.c32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
42 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/u-boot/board/warp/
A Dwarp.c33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/u-boot/board/bachmann/ot1200/
A Dot1200.c36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
49 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
117 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
/u-boot/board/ccv/xpress/
A Dxpress.c35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
43 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/u-boot/arch/arm/include/asm/mach-imx/
A Diomux-v3.h146 #define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) macro
207 #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) macro
226 #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) macro
/u-boot/board/kosagi/novena/
A Dnovena_spl.c34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
53 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
62 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
68 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/u-boot/board/compulab/cm_fx6/
A Dcommon.h11 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
/u-boot/board/freescale/mx6sxsabreauto/
A Dmx6sxsabreauto.c37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
50 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
/u-boot/board/BuR/brppt2/
A Dboard.c56 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
60 #define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
64 #define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
68 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
72 #define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
/u-boot/board/barco/titanium/
A Dtitanium.c30 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/u-boot/board/freescale/mx6sxsabresd/
A Dmx6sxsabresd.c37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
54 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/u-boot/board/menlo/m53menlo/
A Dm53menlo.c148 PAD_CTL_PUS_100K_UP)
384 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
425 PAD_CTL_PUS_100K_UP), in setup_iomux_nand()
427 PAD_CTL_PUS_100K_UP), in setup_iomux_nand()
/u-boot/board/freescale/mx53loco/
A Dmx53loco.c51 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
64 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
/u-boot/board/phytec/pfla02/
A Dpfla02.c38 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
58 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
61 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/u-boot/board/myir/mys_6ulx/
A Dmys_6ulx.c32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \

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