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Searched refs:PCIE (Results 1 – 25 of 32) sorted by relevance

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/u-boot/doc/
A DREADME.srio-pcie-boot-corenet2 SRIO and PCIE Boot on Corenet Platforms
5 For some PowerPC processors with SRIO or PCIE interface, boot location can be
6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
12 platforms and a RCW example with boot from SRIO or PCIE configuration.
14 Environment of the SRIO or PCIE boot:
22 the boot location to SRIO or PCIE, and holdoff all the cores.
27 | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
35 the boot from SRIO or PCIE.
63 SRIO or PCIE port 1.
112 perform the role as a master for boot from SRIO or PCIE.
[all …]
/u-boot/drivers/phy/marvell/
A Dcomphy_a3700.c177 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
182 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up()
187 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); in comphy_pcie_power_up()
192 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
202 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up()
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
219 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
232 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
235 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_pcie_power_up()
240 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0), in comphy_pcie_power_up()
[all …]
A Dcomphy_a3700.h74 PCIE = 1, enumerator
80 if (unit == PCIE) in phy_addr()
/u-boot/board/freescale/lx2160a/
A DREADME88 1 |Mezzanine:X-M4-PCIE-SGMII (29733)
91 |Mezzanine:X-M4-PCIE-SGMII (29733)
98 |Mezzanine:X-M4-PCIE-SGMII (29733)
105 |Mezzanine:X-M4-PCIE-SGMII (29733)
126 |Mezzanine:X-M4-PCIE-SGMII (29733)
133 |Mezzanine:X-M4-PCIE-SGMII (29733)
155 2 |Mezzanine:X-M6-PCIE-X8 (29737) *
163 |Mezzanine:X-M4-PCIE-SGMII (29733)
177 |Mezzanine:X-M4-PCIE-SGMII (29733)
185 2 |Mezzanine:X-M6-PCIE-X8 (29737) *
[all …]
/u-boot/arch/arm/mach-tegra/tegra30/
A Dpinmux.c263 PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
264 PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
265 PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
266 PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
267 PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
268 PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
269 PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
270 PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
271 PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
272 PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
/u-boot/board/avionic-design/common/
A Dpinmux-config-tamonten-ng.h263 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
264 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
265 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
266 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
267 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
272 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/u-boot/board/nvidia/cardhu/
A Dpinmux-config-cardhu.h267 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
272 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
273 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
274 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
275 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
276 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/u-boot/arch/x86/include/asm/arch-apollolake/acpi/
A Dsouthbridge.asl10 /* PCIE device */
/u-boot/configs/
A Dsbc8548_PCI_33_PCIE_defconfig10 CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
A Dsbc8548_PCI_66_PCIE_defconfig10 CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
A DMPC837XERDB_SLAVE_defconfig107 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
A DMPC837XERDB_defconfig148 CONFIG_SYS_EXTRA_OPTIONS="PCIE"
/u-boot/board/toradex/colibri_t30/
A Dpinmux-config-colibri_t30.h283 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
288 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
289 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
290 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
291 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
292 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
293 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
294 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/
A Dfsp-s.txt240 - fsps,pcie-clock-gating-disabled: Enable PCIE Clock Gating
241 - fsps,pcie-root-port8xh-decode: Enable PCIE Root Port 8xh Decode
242 - fsps,pcie8xh-decode-port-index: PCIE 8xh Decode Port Index
244 - fsps,pcie-root-port-peer-memory-write-enable: Enable PCIE Root Port Peer
246 - fsps,pcie-aspm-sw-smi-number: PCIE SWSMI Number
249 - fsps,pcie-rp-hide: Hide PCIE Root Port Configuration Space
250 - fsps,pcie-rp-slot-implemented: PCIE Root Port Slot Implement
252 - fsps,pcie-rp-pm-sci: PCIE PM SCI
253 - fsps,pcie-rp-ext-sync: PCIE Root Port Extended Sync
279 - fsps,pcie-rp-ltr-config-lock: PCIE LTR Lock
[all …]
A Dfsp-m.txt243 - fspm,start-timer-ticker-of-pfet-assert: PCIE SLOT Power Enable Assert Time - PFET
/u-boot/board/freescale/p1_p2_rdb_pc/
A DREADME21 * PCIE slot and mini-PCIE slots
/u-boot/arch/arm/mach-tegra/tegra20/
A Dpinmux.c304 PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
325 PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
328 PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
A Dclock.c334 NONE(PCIE),
/u-boot/arch/arm/dts/
A Dzynqmp-zcu102-revA.dts219 output-low; /* PCIE = 0, DP = 1 */
225 output-high; /* PCIE = 0, DP = 1 */
231 output-high; /* PCIE = 0, USB0 = 1 */
237 output-high; /* PCIE = 0, SATA = 1 */
A Dam57xx-idk-common.dtsi244 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
A Dam5729-beagleboneai.dts290 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
/u-boot/board/toradex/apalis_t30/
A Dpinmux-config-apalis_t30.h300 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
301 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
302 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
303 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
/u-boot/board/hisilicon/poplar/
A DREADME18 PCIE One PCIe 2.0 interfaces
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun50i_h6.c148 MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32); in mctl_set_master_priority()
/u-boot/arch/arm/mach-tegra/tegra114/
A Dclock.c316 NONE(PCIE),

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