Searched refs:PCIEXBAR (Results 1 – 5 of 5) sorted by relevance
| /u-boot/arch/x86/include/asm/arch-broadwell/ |
| A D | pch.h | 17 #define PCIEXBAR 0x60 macro
38 #define PCIEXBAR 0x60 macro
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| /u-boot/arch/x86/cpu/ivybridge/ |
| A D | northbridge.c | 46 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg); in get_pcie_bar()
167 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); in sandybridge_setup_northbridge_bars()
168 dm_pci_write_config32(dev, PCIEXBAR + 4, in sandybridge_setup_northbridge_bars()
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| /u-boot/arch/x86/cpu/broadwell/ |
| A D | northbridge.c | 116 dm_pci_write_config32(dev, PCIEXBAR + 4, 0); in broadwell_northbridge_early_init()
118 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); in broadwell_northbridge_early_init()
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| /u-boot/arch/x86/include/asm/arch-ivybridge/ |
| A D | sandybridge.h | 52 #define PCIEXBAR 0x60 macro
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| /u-boot/arch/x86/cpu/apollolake/ |
| A D | hostbridge.c | 33 PCIEXBAR = 0x60, enumerator
174 pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32); in apl_hostbridge_early_init()
191 pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32); in apl_hostbridge_early_init()
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