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Searched refs:PCI_SIZE_32 (Results 1 – 19 of 19) sorted by relevance

/u-boot/arch/x86/cpu/ivybridge/
A Dcpu.c111 PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32); in enable_usb_bar()
112 pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32); in enable_usb_bar()
114 pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32); in enable_usb_bar()
118 PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32); in enable_usb_bar()
119 pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32); in enable_usb_bar()
121 pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32); in enable_usb_bar()
125 PCH_XHCI_TEMP_BAR0, PCI_SIZE_32); in enable_usb_bar()
126 pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32); in enable_usb_bar()
128 pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32); in enable_usb_bar()
/u-boot/cmd/
A Dpci.c39 case PCI_SIZE_32: in pci_byte_size()
77 case PCI_SIZE_32: in pci_read_config()
183 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
188 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
189 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
190 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
191 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
192 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
205 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
663 enum pci_size_t size = PCI_SIZE_32; in do_pci()
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/u-boot/arch/x86/cpu/apollolake/
A Dlpc.c39 &lgir, PCI_SIZE_32); in find_unused_pmio_window()
77 PCI_SIZE_32); in lpc_open_pmio_window()
94 PCI_SIZE_32); in lpc_open_pmio_window()
A Dhostbridge.c166 pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32); in apl_hostbridge_early_init()
168 pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32); in apl_hostbridge_early_init()
174 pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32); in apl_hostbridge_early_init()
191 pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32); in apl_hostbridge_early_init()
199 pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32); in apl_hostbridge_early_init()
A Dpmc.c174 PCI_SIZE_32); in enable_pmcbar()
175 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); in enable_pmcbar()
177 PCI_SIZE_32); in enable_pmcbar()
178 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32); in enable_pmcbar()
A Duart.c60 pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32); in apl_uart_init()
64 PCI_COMMAND_MASTER, PCI_SIZE_32); in apl_uart_init()
A Dcpu_spl.c75 PCI_SIZE_32); in p2sb_enable_bar()
76 pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); in p2sb_enable_bar()
/u-boot/arch/x86/cpu/intel_common/
A Dfast_spi.c53 pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32); in fast_spi_get_bios_mmap()
65 PCI_SIZE_32); in fast_spi_early_init()
A Dp2sb.c67 PCI_SIZE_32); in p2sb_early_init()
68 pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); in p2sb_early_init()
/u-boot/arch/x86/cpu/
A Dpci.c31 case PCI_SIZE_32: in pci_x86_read_config()
50 case PCI_SIZE_32: in pci_x86_write_config()
/u-boot/arch/sandbox/lib/
A Dpci_io.c100 ret = pci_io_read(addr, &value, PCI_SIZE_32); in _inl()
127 pci_io_write(addr, value, PCI_SIZE_32); in _outl()
/u-boot/drivers/pci/
A Dpci-uclass.c295 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32); in pci_bus_clrset_config32()
301 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32); in pci_bus_clrset_config32()
330 return pci_write_config(bdf, offset, value, PCI_SIZE_32); in pci_write_config32()
355 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32); in dm_pci_write_config32()
398 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); in pci_read_config32()
463 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32); in dm_pci_read_config32()
583 case PCI_SIZE_32: in pci_generic_mmap_write_config()
614 case PCI_SIZE_32: in pci_generic_mmap_read_config()
833 PCI_SIZE_32); in pci_bind_bus_devices()
852 &val, PCI_SIZE_32); in pci_bind_bus_devices()
A Dpcie_fsl.c75 case PCI_SIZE_32: in fsl_pcie_read_config()
112 case PCI_SIZE_32: in fsl_pcie_write_config()
172 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32); in fsl_pcie_hose_read_config_dword()
193 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32); in fsl_pcie_hose_write_config_dword()
A Dpci_octeontx.c82 case PCI_SIZE_32: in readl_size()
102 case PCI_SIZE_32: in writel_size()
A Dpcie_layerscape_gen4.c254 case PCI_SIZE_32: in ls_pcie_g4_read_config()
284 case PCI_SIZE_32: in ls_pcie_g4_write_config()
A Dpcie_intel_fpga.c168 *value = pci_get_ff(PCI_SIZE_32); in tlp_read_packet()
A Dpcie_iproc.c618 bdf, offset, &data, PCI_SIZE_32); in iproc_pcie_config_read32()
644 if (size == PCI_SIZE_32) { in iproc_pcie_config_write32()
/u-boot/drivers/video/
A Dbroadwell_igd.c564 PCI_SIZE_32); in systemagent_revision()
/u-boot/include/
A Dpci.h895 PCI_SIZE_32, enumerator

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