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Searched refs:PE (Results 1 – 9 of 9) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c848 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
1100 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1113 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1114 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1118 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1135 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1151 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1152 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1157 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
A Dddr3_hw_training.h118 #define PE 4 macro
/u-boot/board/freescale/p2041rdb/
A DREADME47 Use PE tool to produce a image used to be programed to
70 Use PE tool to produce a image used to be programed to
/u-boot/arch/arm/dts/
A Dsun50i-a64-bananapi-m64.dts211 * This regulator also drives the PE pingroup GPIOs,
A Dsun7i-a20-bananapi.dts222 /* PE */
/u-boot/arch/arm/mach-tegra/tegra124/
A Dpinmux.c273 PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4),
/u-boot/board/cei/cei-tk1-som/
A Dpinmux-config-cei-tk1-som.h254 PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
/u-boot/board/nvidia/jetson-tk1/
A Dpinmux-config-jetson-tk1.h262 PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
/u-boot/doc/uefi/
A Duefi.rst64 or the network adapter and the file name of the most recently loaded PE-COFF

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