Searched refs:PE (Results 1 – 9 of 9) sorted by relevance
/u-boot/drivers/ddr/marvell/axp/ |
A D | ddr3_read_leveling.c | 848 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode() 1100 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode() 1113 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode() 1114 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode() 1118 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode() 1135 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode() 1151 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode() 1152 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode() 1157 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
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A D | ddr3_hw_training.h | 118 #define PE 4 macro
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/u-boot/board/freescale/p2041rdb/ |
A D | README | 47 Use PE tool to produce a image used to be programed to 70 Use PE tool to produce a image used to be programed to
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/u-boot/arch/arm/dts/ |
A D | sun50i-a64-bananapi-m64.dts | 211 * This regulator also drives the PE pingroup GPIOs,
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A D | sun7i-a20-bananapi.dts | 222 /* PE */
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/u-boot/arch/arm/mach-tegra/tegra124/ |
A D | pinmux.c | 273 PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4),
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/u-boot/board/cei/cei-tk1-som/ |
A D | pinmux-config-cei-tk1-som.h | 254 PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
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/u-boot/board/nvidia/jetson-tk1/ |
A D | pinmux-config-jetson-tk1.h | 262 PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
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/u-boot/doc/uefi/ |
A D | uefi.rst | 64 or the network adapter and the file name of the most recently loaded PE-COFF
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