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Searched refs:PERF_SOFT_RST (Results 1 – 9 of 9) sorted by relevance

/u-boot/arch/mips/mach-mscc/
A Dreset.c37 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
55 (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
65 writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
/u-boot/board/mscc/ocelot/
A Docelot.c35 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in mscc_switch_reset()
37 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, in mscc_switch_reset()
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton_devcpu_gcb.h10 #define PERF_SOFT_RST 0x90 macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval_devcpu_gcb.h14 #define PERF_SOFT_RST 0x8 macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2_devcpu_gcb.h13 #define PERF_SOFT_RST 0x8 macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot_devcpu_gcb.h10 #define PERF_SOFT_RST 0x8 macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt_devcpu_gcb.h12 #define PERF_SOFT_RST 0x8 macro
/u-boot/drivers/net/mscc_eswitch/
A Dserval_switch.c416 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in serval_stop()
/u-boot/arch/mips/mach-mscc/include/mach/
A Dddr.h444 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); in hal_vcoreiii_ddr_failed()

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