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Searched refs:PERI_ACLK_HZ (Results 1 – 12 of 12) sorted by relevance

/u-boot/drivers/clk/rockchip/
A Dclk_rk3128.c208 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
209 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
211 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
213 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
215 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
217 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()
368 return DIV_TO_RATE(PERI_ACLK_HZ, div); in rk3128_peri_get_pclk()
375 src_clk_div = PERI_ACLK_HZ / hz; in rk3128_peri_set_pclk()
392 return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div); in rk3128_peri_set_pclk()
A Dclk_rk3036.c147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
154 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
156 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()
A Dclk_rk322x.c149 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
150 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
152 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
154 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
156 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
158 PERI_ACLK_HZ && pclk_div < 0x8); in rkclk_init()
A Dclk_rk3188.c432 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
433 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
435 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
437 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
439 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
441 PERI_ACLK_HZ && (pclk_div < 0x4)); in rkclk_init()
A Dclk_rk3288.c476 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
477 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
479 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
481 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
483 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); in rkclk_init()
485 PERI_ACLK_HZ && (pclk_div < 0x4)); in rkclk_init()
A Dclk_rk3308.c1002 rk3308_peri_set_clk(priv, ACLK_PERI, PERI_ACLK_HZ); in rk3308_clk_init()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dcru_rk3188.h21 #define PERI_ACLK_HZ 148500000 macro
A Dcru_rk3036.h20 #define PERI_ACLK_HZ 148500000 macro
A Dcru_rk3128.h26 #define PERI_ACLK_HZ 148500000 macro
A Dcru_rk322x.h21 #define PERI_ACLK_HZ 148500000 macro
A Dcru_rk3288.h23 #define PERI_ACLK_HZ 148500000 macro
/u-boot/arch/arm/include/asm/arch-rk3308/
A Dcru_rk3308.h20 #define PERI_ACLK_HZ 200000000 macro

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