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Searched refs:PINMUX_CFG_REG (Results 1 – 15 of 15) sorted by relevance

/u-boot/drivers/pinctrl/renesas/
A Dpfc-r8a77995.c2380 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2414 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2448 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2482 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2516 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2550 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2584 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
2623 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2633 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2643 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
[all …]
A Dpfc-r8a77970.c2076 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2110 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2144 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2178 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2212 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2246 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2285 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2295 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2305 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2315 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
[all …]
A Dpfc-r8a7792.c1994 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
2028 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2062 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2096 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2130 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2164 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2198 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
2232 { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
2266 { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
2300 { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
[all …]
A Dpfc-r8a77980.c2478 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2512 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2546 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2580 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2614 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2648 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2687 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2697 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2707 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2717 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
[all …]
A Dpfc-r8a77990.c4535 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4569 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4603 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4637 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4671 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4705 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4739 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4778 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4788 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4798 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
[all …]
A Dpfc-r8a7795.c5132 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5166 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5200 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5234 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5268 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5302 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5336 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5370 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5409 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5419 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
[all …]
A Dpfc-r8a7796.c5045 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5079 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5113 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5147 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5181 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5215 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5249 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5283 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5322 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5332 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
[all …]
A Dpfc-r8a77965.c5341 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5375 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5409 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5443 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5477 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5511 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5545 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5579 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5618 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5628 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
[all …]
A Dpfc-r8a7791.c5434 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5468 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5502 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5536 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5570 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5604 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5638 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
5672 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
A Dpfc-r8a7794.c4622 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4656 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4690 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4724 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4758 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4792 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4826 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
A Dsh_pfc.h137 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ macro
A Dpfc-r8a7790.c4748 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4782 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4816 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4850 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4884 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4918 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
/u-boot/include/
A Dsh_pfc.h51 #define PINMUX_CFG_REG(name, r, r_width, f_width) \ macro
186 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
/u-boot/arch/arm/mach-rmobile/
A Dpfc-r8a7740.c2341 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2368 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2381 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2400 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
A Dpfc-sh73a0.c2523 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
2558 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2593 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {

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