Searched refs:PLL1 (Results 1 – 7 of 7) sorted by relevance
| /u-boot/doc/device-tree-bindings/clock/ |
| A D | ti,cdce9xx.txt | 28 For all PLL1, PLL2, ... an optional child node can be used to specify spread
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| A D | st,stm32mp1.txt | 86 each PLL children nodes for PLL1 to PLL4 (see ref manual for details)
90 For PLL1, when the node is absent, the frequency of the OPP node is used
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| /u-boot/include/dt-bindings/clock/ |
| A D | stm32mp1-clks.h | 183 #define PLL1 176 macro
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| /u-boot/doc/ |
| A D | README.Heterogeneous-SoCs | 54 Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
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| /u-boot/drivers/video/tegra124/ |
| A D | sor.c | 565 DUMP_REG(PLL1); in dump_sor_reg()
724 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | in tegra_dc_sor_enable_dp()
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| A D | sor.h | 251 #define PLL1 0x18 macro
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| /u-boot/doc/board/sipeed/ |
| A D | maix.rst | 527 including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
541 instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of
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