Home
last modified time | relevance | path

Searched refs:PLL3 (Results 1 – 5 of 5) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dstm32mp1-clks.h185 #define PLL3 178 macro
/u-boot/doc/
A DREADME.Heterogeneous-SoCs55 PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
/u-boot/drivers/video/tegra124/
A Dsor.c567 DUMP_REG(PLL3); in dump_sor_reg()
708 tegra_sor_write_field(sor, PLL3, in tegra_dc_sor_enable_dp()
A Dsor.h282 #define PLL3 0x1a macro
/u-boot/doc/device-tree-bindings/clock/
A Dst,stm32mp1.txt26 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2

Completed in 12 milliseconds